Abstract: A gas mixing system for semiconductor fabrication includes a mixing block. The mixing block defines a gas mixing chamber, a first gas channel fluidly coupled to the gas mixing chamber at a first exit location, and a second gas channel fluidly coupled to the gas mixing chamber at a second exit location, wherein the first exit location is diametrically opposite the second exit location relative to the gas mixing chamber and the second gas channel has a bend of 90 degrees or less between an entrance of the second gas channel and the second exit location.

Abstract: An image sensor device includes a transistor disposed in a pixel region; a salicide block layer covering the pixel region; a first ILD layer covering the salicide block layer; a second ILD layer on the first ILD layer; a source contacts extending through the second and first ILD layers and the salicide block layer, and including first polysilicon plug in the first ILD layer and first conductive metal layer on the first polysilicon plug; and a drain contact extending through the second and first ILD layers and the salicide block, and including second polysilicon plug in the first ILD layer and second conductive metal layer on the second polysilicon plug.

Abstract: A gas mixing system for semiconductor fabrication includes a mixing block. The mixing block defines a gas mixing chamber, a first gas channel fluidly coupled to the gas mixing chamber at a first exit location, and a second gas channel fluidly coupled to the gas mixing chamber at a second exit location, wherein the first exit location is diametrically opposite the second exit location relative to the gas mixing chamber and the second gas channel has a bend of 90 degrees or less between an entrance of the second gas channel and the second exit location.

Abstract: A height adjustable semiconductor wafer support is provided. The height adjustable semiconductor wafer support includes a chuck for supporting a semiconductor wafer, an adjustment mechanism having a top surface for supporting the chuck, and a stage coupled to the adjustment mechanism such that movement of the top surface of the adjustment mechanism relative to the stage changes a distance between the top surface of the adjustment mechanism and a top surface of the stage.

Abstract: A gas mixing system for semiconductor fabrication includes a mixing block. The mixing block defines a gas mixing chamber, a first gas channel fluidly coupled to the gas mixing chamber at a first exit location, and a second gas channel fluidly coupled to the gas mixing chamber at a second exit location, wherein the first exit location is diametrically opposite the second exit location relative to the gas mixing chamber and the second gas channel has a bend of 90 degrees or less between an entrance of the second gas channel and the second exit location.

Abstract: An all-around curved polarizer for an all-around curved display device comprises a polarizing layer, a first protective layer and a second protective layer. The first protective layer is arranged on a side of the polarizing layer adjacent to the all-around curved display device and has a first coefficient of thermal expansion. The second protective layer is disposed on the other side of the polarizing layer opposite to the all-around curved display device, and has a second coefficient of thermal expansion, and the second coefficient of thermal expansion is greater than the first coefficient of thermal expansion of the first protective layer.

Abstract: A height adjustable semiconductor wafer support is provided. The height adjustable semiconductor wafer support includes a chuck for supporting a semiconductor wafer, an adjustment mechanism having a top surface for supporting the chuck, and a stage coupled to the adjustment mechanism such that movement of the top surface of the adjustment mechanism relative to the stage changes a distance between the top surface of the adjustment mechanism and a top surface of the stage.

Abstract: An image sensor device includes a transistor disposed in a pixel region; a salicide block layer covering the pixel region; a first ILD layer covering the salicide block layer; a second ILD layer on the first ILD layer; a source contacts extending through the second and first ILD layers and the salicide block layer, and including first polysilicon plug in the first ILD layer and first conductive metal layer on the first polysilicon plug; and a drain contact extending through the second and first ILD layers and the salicide block, and including second polysilicon plug in the first ILD layer and second conductive metal layer on the second polysilicon plug.

Abstract: An all-around curved polarizer for an all-around curved display device comprises a polarizing layer, a first protective layer and a second protective layer. The first protective layer is arranged on a side of the polarizing layer adjacent to the all-around curved display device and has a first coefficient of thermal expansion. The second protective layer is disposed on the other side of the polarizing layer opposite to the all-around curved display device, and has a second coefficient of thermal expansion, and the second coefficient of thermal expansion is greater than the first coefficient of thermal expansion of the first protective layer.

Abstract: An image sensor device includes a transistor disposed in a pixel region; a salicide block layer covering the pixel region; a first ILD layer covering the salicide block layer; a second ILD layer on the first ILD layer; a source contacts extending through the second and first ILD layers and the salicide block layer, and including first polysilicon plug in the first ILD layer, first self-aligned silicide layer on the polysilicon plug and first conductive metal layer on the first self-aligned silicide layer; and a drain contact extending through the second and first ILD layers and the salicide block, and including second polysilicon plug in first ILD layer, second self-aligned silicide layer on the second polysilicon plug, and second conductive metal layer on the second self-aligned silicide layer.

Abstract: A method for fabricating flash memory is provided. A plurality of floating gate structures is formed on a gate dielectric layer in the memory device region of a substrate. The protective spacers are formed on two opposite sidewalls of each floating gate structure. A polysilicon gate structures are formed on the logic device region and a polysilicon control gate structure with an opening are formed on the memory device region to cover two adjacent floating gate structures, wherein the two protective spacers facing each other between two adjacent floating gate structures are exposed by the opening, and then the exposed protective spacer are removed. An ion implantation is performed on the substrate to form a source region between the two adjacent floating gate structures on each cell area. There will be no polysilicon material residue in the memory device region or pitting/undercutting phenomenon in the logic device region.

Abstract: A method for fabricating flash memory is provided. A plurality of floating gate structures is formed on a gate dielectric layer in the memory device region of a substrate. The protective spacers are formed on two opposite sidewalls of each floating gate structure. A polysilicon gate structures are formed on the logic device region and a polysilicon control gate structure with an opening are formed on the memory device region to cover two adjacent floating gate structures, wherein the two protective spacers facing each other between two adjacent floating gate structures are exposed by the opening, and then the exposed protective spacer are removed. An ion implantation is performed on the substrate to form a source region between the two adjacent floating gate structures on each cell area. There will be no polysilicon material residue in the memory device region or pitting/undercutting phenomenon in the logic device region.

Abstract: A height adjustable semiconductor wafer support is provided. The height adjustable semiconductor wafer support includes a chuck for supporting a semiconductor wafer, an adjustment mechanism having a top surface for supporting the chuck, and a stage coupled to the adjustment mechanism such that movement of the top surface of the adjustment mechanism relative to the stage changes a distance between the top surface of the adjustment mechanism and a top surface of the stage.

Abstract: An image sensor device includes a transistor disposed in a pixel region; a salicide block layer covering the pixel region; a first ILD layer covering the salicide block layer; a second ILD layer on the first ILD layer; a source contacts extending through the second and first ILD layers and the salicide block layer, and including first polysilicon plug in the first ILD layer, first self-aligned silicide layer on the polysilicon plug and first conductive metal layer on the first self-aligned silicide layer; and a drain contact extending through the second and first ILD layers and the salicide block, and including second polysilicon plug in first ILD layer, second self-aligned silicide layer on the second polysilicon plug, and second conductive metal layer on the second self-aligned silicide layer.

Abstract: A gas mixing system for semiconductor fabrication includes a mixing block. The mixing block defines a gas mixing chamber, a first gas channel fluidly coupled to the gas mixing chamber at a first exit location, and a second gas channel fluidly coupled to the gas mixing chamber at a second exit location, wherein the first exit location is diametrically opposite the second exit location relative to the gas mixing chamber and the second gas channel has a bend of 90 degrees or less between an entrance of the second gas channel and the second exit location.

Abstract: The present invention provides a class of novel aryl pseudo-C-glycoside compounds that are effective for treating diabetes. Also provided are methods for making such compounds and methods for treating diabetes by administering such compounds to patients who have been diagnosed with diabetes or are at risk of developing diabetes.

Abstract: A planarization process includes the following steps. A first dielectric layer and a second dielectric layer are sequentially formed to conformally cover a pattern in a cell area and a substrate in the cell area and an isolation area, thereby the first dielectric layer and the second dielectric layer having a dishing in the isolation area. A dummy material is formed in the dishing and exposes a part of the second dielectric layer right above the pattern. A first removing process is performed to remove the exposed part of the second dielectric layer. The dummy material is removed. A second removing process is performed to remove an exposed part of the first dielectric layer by using the second dielectric layer as an etch stop layer. A third removing process is performed to remove the second dielectric layer and the first dielectric layer.

Abstract: A semiconductor memory device includes a first inverter, a second inverter, a first and second inner access transistors, and a first and second outer access transistors. The first inverter includes a first pull-up transistor and a first pull-down transistor, the second inverter includes a second pull-up transistor (PL2) and a second pull-down transistor, and the first inverter and the second inverter forms a latch circuit. The first and second inner access transistors and the first and second outer access transistors are electrically connected to the latch circuit, and channel widths of the second inner access transistor and the second outer access transistor are different from each other.

Abstract: The present invention provides a class of novel aryl pseudo-C-glycoside compounds that are effective for treating diabetes. Also provided are methods for making such compounds and methods for treating diabetes by administering such compounds to patients who have been diagnosed with diabetes or are at risk of developing diabetes.

Abstract: A lateral-diffused metal oxide semiconductor device including a substrate, a second deep well, a gate, a source, a drain and a first dopant region is provided. The substrate includes a first deep well having a first conductive type. The second deep well having a second conductive type is disposed in the first deep well. The gate is disposed on the substrate and the boundary of the first and the second deep well. The source and the drain having a second conductive type are disposed beside the gate and in the first deep well and the second deep well respectively. The first dopant region having a first conductive type is disposed in the second deep well, wherein the first dopant region is separated from the drain. Moreover, a method for fabricating said lateral-diffused metal oxide semiconductor device is also provided.