Patents by Inventor Ming Shing
Ming Shing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160372554Abstract: A lateral-diffused metal oxide semiconductor device including a substrate, a second deep well, a gate, a source, a drain and a first dopant region is provided. The substrate includes a first deep well having a first conductive type. The second deep well having a second conductive type is disposed in the first deep well. The gate is disposed on the substrate and the boundary of the first and the second deep well. The source and the drain having a second conductive type are disposed beside the gate and in the first deep well and the second deep well respectively. The first dopant region having a first conductive type is disposed in the second deep well, wherein the first dopant region is separated from the drain. Moreover, a method for fabricating said lateral-diffused metal oxide semiconductor device is also provided.Type: ApplicationFiled: August 31, 2016Publication date: December 22, 2016Inventors: Ming-Shing Chen, Wei-Ting Wu, Ming-Hui Chang, Chao-Chun Ning
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Patent number: 9490360Abstract: Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided.Type: GrantFiled: February 19, 2014Date of Patent: November 8, 2016Assignee: United Microelectronics Corp.Inventors: Ming-Shing Chen, Ming-Hui Chang, Wei-Ting Wu, Ying-Chou Lai, Horng-Nan Chern, Chorng-Lih Young, Chin-Sheng Yang
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Patent number: 9478457Abstract: Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed.Type: GrantFiled: December 2, 2015Date of Patent: October 25, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Ming-Shing Chen, Yu-Ting Wang, Ming-Hui Chang
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Patent number: 9461166Abstract: A lateral-diffused metal oxide semiconductor device including a substrate, a second deep well, a gate, a source, a drain and a first dopant region is provided. The substrate includes a first deep well having a first conductive type. The second deep well having a second conductive type is disposed in the first deep well. The gate is disposed on the substrate and the boundary of the first and the second deep well. The source and the drain having a second conductive type are disposed beside the gate and in the first deep well and the second deep well respectively. The first dopant region having a first conductive type is disposed in the second deep well, wherein the first dopant region is separated from the drain. Moreover, a method for fabricating said lateral-diffused metal oxide semiconductor device is also provided.Type: GrantFiled: November 5, 2013Date of Patent: October 4, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Shing Chen, Wei-Ting Wu, Ming-Hui Chang, Chao-Chun Ning
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Patent number: 9385236Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a plurality of fin shaped structures and a dummy gate structure. The fin shaped structures are disposed in a substrate, where at least one of the fin shaped structures has a tipped end. The dummy gate structure is disposed on the substrate, and includes an extending portion covering the tipped end.Type: GrantFiled: June 24, 2015Date of Patent: July 5, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chien-Ying Sun, En-Chiuan Liou, Ming-Shing Chen, Yu-Cheng Tung, Chih-Wei Yang
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Patent number: 9379237Abstract: A LDMOS includes a gate structure disposed on the surface of a semiconductor substrate, a source region having a first conductivity type, a drain region having the first conductivity type, an isolation region surrounding the source/drain regions, a doped region having a second conductivity type, and a base region having the second conductivity type formed in the doped region. The source/drain regions are respectively disposed on two sides of the gate structure. The doped region surrounds the isolation region, and the bottom of the doped region is deeper than the bottom of the isolation region. The base region is disposed at the surface of the semiconductor substrate.Type: GrantFiled: January 22, 2015Date of Patent: June 28, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Hui Chang, Wei-Ting Wu, Ming-Shing Chen
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Publication number: 20160086843Abstract: Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed.Type: ApplicationFiled: December 2, 2015Publication date: March 24, 2016Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Ming-Shing Chen, Yu-Ting Wang, Ming-Hui Chang
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Publication number: 20160027683Abstract: Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method include steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited covering the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removing by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate selectively is removed.Type: ApplicationFiled: August 12, 2014Publication date: January 28, 2016Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Ming-Shing Chen, Yu-Ting Wang, Ming-Hui Chang
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Patent number: 9236289Abstract: Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method include steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited covering the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removing by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate selectively is removed.Type: GrantFiled: August 12, 2014Date of Patent: January 12, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Ming-Shing Chen, Yu-Ting Wang, Ming-Hui Chang
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Publication number: 20150236150Abstract: Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided.Type: ApplicationFiled: February 19, 2014Publication date: August 20, 2015Applicant: United Microelectronics Corp.Inventors: Ming-Shing Chen, Ming-Hui Chang, Wei-Ting Wu, Ying-Chou Lai, Horng-Nan Chern, Chorng-Lih Young, Chin-Sheng Yang
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Publication number: 20150123197Abstract: A lateral-diffused metal oxide semiconductor device including a substrate, a second deep well, a gate, a source, a drain and a first dopant region is provided. The substrate includes a first deep well having a first conductive type. The second deep well having a second conductive type is disposed in the first deep well. The gate is disposed on the substrate and the boundary of the first and the second deep well. The source and the drain having a second conductive type are disposed beside the gate and in the first deep well and the second deep well respectively. The first dopant region having a first conductive type is disposed in the second deep well, wherein the first dopant region is separated from the drain. Moreover, a method for fabricating said lateral-diffused metal oxide semiconductor device is also provided.Type: ApplicationFiled: November 5, 2013Publication date: May 7, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ming-Shing Chen, Wei-Ting Wu, Ming-Hui Chang, Chao-Chun Ning
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Publication number: 20150103585Abstract: A Static Random Access Memory (SRAM) cell is a latch circuit formed with two inverters each formed with a PMOS transistor and an NMOS transistor. The latch circuit is coupled to a capacitor through a switch. When the switch is switched on, the stability of data stored in the SRAM cell will be enhanced. When the switch is switched off, data can be written to the SRAM cell quickly.Type: ApplicationFiled: October 11, 2013Publication date: April 16, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Young-Ran Chuang, Chao-Hsien Wu, Ming-Shing Chen
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Patent number: 9000455Abstract: A shadow mask assembly includes a securing assembly configured to hold a substrate that is configured to hold a plurality of dies. The securing assembly includes a number of guide pins and a shadow mask comprising holes for the guide pins, said holes allowing the guide pins freedom of motion in one direction. The securing assembly includes a number of embedded magnets configured to secure the shadow mask to the securing assembly.Type: GrantFiled: March 10, 2013Date of Patent: April 7, 2015Assignee: TSMC Solid State Lighting Ltd.Inventors: Ming-Shing Lee, Chyi-Shyuan Chern, Hsin-Hsien Wu, Yung-Chang Chen, Ming-Hua Lo, Chu-Ching Tsai
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Patent number: 8889440Abstract: An optical emitter includes a Light-Emitting Diode (LED) on a package wafer, transparent insulators, and one or more transparent electrical connectors between the LED die and one or more contact pads on the packaging wafer. The transparent insulators are deposited on the package wafer with LED dies attached using a lithography or a screen printing method. The transparent electrical connectors are deposited using physical vapor deposition, chemical vapor deposition, spin coating, spray coating, or screen printing and may be patterned using a lithography process and etching.Type: GrantFiled: December 11, 2013Date of Patent: November 18, 2014Assignee: TSMC Solid State Lighting Ltd.Inventors: Yung-Chang Chen, Hsin-Hsien Wu, Ming Shing Lee, Huai-En Lai, Fu-Wen Liu, Andy Wu
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Publication number: 20140252380Abstract: A shadow mask assembly includes a securing assembly configured to hold a substrate that is configured to hold a plurality of dies. The securing assembly includes a number of guide pins and a shadow mask comprising holes for the guide pins, said holes allowing the guide pins freedom of motion in one direction. The securing assembly includes a number of embedded magnets configured to secure the shadow mask to the securing assembly.Type: ApplicationFiled: March 10, 2013Publication date: September 11, 2014Applicant: TSMC Solid State Lighting Ltd.Inventors: Ming-Shing Lee, Chyi-Shyuan Chern, Hsin-Hsien Wu, Yung-Chang Chen, Ming-Hua Lo, Chu-Ching Tsai
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Publication number: 20140093990Abstract: An optical emitter includes a Light-Emitting Diode (LED) on a package wafer, transparent insulators, and one or more transparent electrical connectors between the LED die and one or more contact pads on the packaging wafer. The transparent insulators are deposited on the package wafer with LED dies attached using a lithography or a screen printing method. The transparent electrical connectors are deposited using physical vapor deposition, chemical vapor deposition, spin coating, spray coating, or screen printing and may be patterned using a lithography process and etching.Type: ApplicationFiled: December 11, 2013Publication date: April 3, 2014Applicant: TSMC Solid State Lighting Ltd.Inventors: Yung-Chang Chen, Hsin-Hsien Wu, Ming Shing Lee, Huai-En Lai, Fu-Wen Liu, Andy Wu
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Patent number: 8610161Abstract: An optical emitter includes a Light-Emitting Diode (LED) on a package wafer, transparent insulators, and one or more transparent electrical connectors between the LED die and one or more contact pads on the packaging wafer. The transparent insulators are deposited on the package wafer with LED dies attached using a lithography or a screen printing method. The transparent electrical connectors are deposited using physical vapor deposition, chemical vapor deposition, spin coating, spray coating, or screen printing and may be patterned using a lithography process and etching.Type: GrantFiled: October 5, 2011Date of Patent: December 17, 2013Assignee: TSMC Solid State Lighting Ltd.Inventors: Yung-Chang Chen, Hsin-Hsien Wu, Ming Shing Lee, Huai-En Lai, Fu-Wen Liu, Andy Wu
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Publication number: 20130332658Abstract: The present invention discloses a data storage system using a solid state disk to replace a non-volatile memory. The data storage system comprises a plurality of controllers, a first storage unit and a second storage unit. The plurality of controllers are electrically connected with each other, and are capable of storing data into said storage units and restoring data from said storage units. When a controller receives the data transmitted from a remote device, a data journal is generated and stored into the first storage unit. After a message of “successfully received” is sent back to the remote device, the data is transferred to the second storage unit.Type: ApplicationFiled: October 23, 2012Publication date: December 12, 2013Applicant: QNAP SYSTEMS, INC.Inventors: Chien-Hung Yang, Ming-Shing Su, Shang-Cheng Yeh
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Publication number: 20120305956Abstract: The present disclosure provides a method of patterning a phosphor layer on a light emitting diode (LED) emitter. The method includes providing at least one LED emitter disposed on a substrate; forming a polymer layer over the at least one LED emitter; providing a mask over the polymer layer and the at least one LED emitter; etching the polymer layer through the mask to expose the at least one LED emitter within a cavity having polymer layer walls; and coating the at least one LED emitter with phosphor.Type: ApplicationFiled: June 1, 2011Publication date: December 6, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Wen Liu, Chyi Shyuan Chern, Hsin-Hsien Wu, Yung-Chang Chen, Ming Shing Lee, Tzu-Wen Shih, Hsin-Hung Chen
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Patent number: D725241Type: GrantFiled: July 15, 2013Date of Patent: March 24, 2015Assignee: Metalchef Equipment LimitedInventor: Ming Shing Lo