Abstract: A water receiving in an air conditioner is disclosed. Further, a water-receiving tray structure for an indoor unit of an air conditioner, an indoor unit and an air conditioner. The water-receiving tray structure includes a water-receiving tray, an elevating member and a fixed member; the indoor unit having a casing with a first end defining a return-air inlet and a second end opposite to the first end and defining the air outlet, the water-receiving tray being arranged in a direction from the return-air inlet to the air outlet and being located below a heat exchanger of the indoor unit; the elevating member being arranged at an air outlet end of the indoor unit and supporting an air outlet side of the water-receiving tray; the fixed member being arranged in the indoor unit and being connected to an air outlet side of the indoor unit.

Abstract: The present disclosure relates to a field of air blowing technologies of evaporators, more particularly to an evaporator baffle structure, an evaporator and an air conditioner. The evaporator baffle structure is configured as a V-shaped structure, in which two branches of the V-shaped structure are provided with a length-adjustable baffle separately, and a side of the V-shaped structure away from an opening thereof is provided with an evaporator mounting member. The evaporator includes an evaporator body and an evaporator baffle structure, in which the evaporator body is configured as an A-shaped structure, and the evaporator baffle structure is disposed at a top end of the evaporator body. The air conditioner includes the evaporator.

Abstract: A piezoelectric energy harvesting apparatus includes a housing and a piezoelectric module disposed in the housing. The piezoelectric module includes a piezoelectric wafer unit and a clamp unit clamping the piezoelectric wafer unit. A resilient member is connected between the clamp unit and an inner wall of the housing to transmit an oscillation movement to the clamp unit, which in turn causes oscillation of the piezoelectric wafer unit for generating an electric power. An impact unit extends movably into the housing and is capable of pushing the clamp unit against the resilient member when being subjected to an ambient natural force such that the resilient member generates the oscillation movement.

Abstract: The present invention relates to the technical field of medicinal chemistry, and in particular discloses a 2-oxo-1,2-dihydrobenzo[cd]indole compound and use thereof. The compound and pharmaceutically acceptable salt, isomer, racemate, prodrug, co-crystallized complex, hydrate, and solvate thereof can effectively inhibit the BET bromodomain receptor, and can be used for preparing a medicine for treating cancers, cell proliferative disorders, inflammatory diseases, and autoimmune disorders, sepsis, and viral infections.

Abstract: A method for forming an integrated circuit includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.

Abstract: An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.

Abstract: Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

Abstract: An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type.

Abstract: A method comprises forming a plurality of interconnect components over a gate structure, wherein a bottom metal line of the interconnect components is connected to the gate structure through a gate plug, depositing a dielectric layer over a top metal line of the interconnect components, forming an opening in the dielectric layer, depositing a first barrier layer on a bottom and sidewalls of the opening using a non-plasma based deposition process, depositing a second barrier layer over the first barrier layer using a plasma based deposition process and forming a pad in the opening.

Abstract: An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type.

Abstract: A piezoelectric energy harvesting apparatus includes a housing and a piezoelectric module disposed in the housing. The piezoelectric module includes a piezoelectric wafer unit and a clamp unit clamping the piezoelectric wafer unit. A resilient member is connected between the clamp unit and an inner wall of the housing to transmit an oscillation movement to the clamp unit, which in turn causes oscillation of the piezoelectric wafer unit for generating an electric power. An impact unit extends movably into the housing and is capable of pushing the clamp unit against the resilient member when being subjected to an ambient natural force such that the resilient member generates the oscillation movement.

Abstract: Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

Abstract: A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials.

Abstract: A method of calculating voltage and power of large-scaled photovoltaic power plant includes following steps. Environment models of varies locations within the photovoltaic power plant are obtained. A photovoltaic display model is established by establishing a photovoltaic cell model, combining the photovoltaic cell model with the environment models, determining a combination of the environmental data on photovoltaic panels and the photovoltaic cell model, and determining a quantitative relationship between a photovoltaic cell power generation state and photovoltaic environment. An inverter model is obtained by modeling inverters connected to photovoltaic cells. A grid-side model is obtained. An electrical energy and voltage forecast model is constructed by integrated the photovoltaic display model, the inverter model, and the grid-side model.

Abstract: The invention provides a plurality of embryonic stem cell-like progenitor cells, which are isolated from a human tissue by a systemic screening of human mesenchymal stromal stem/progenitor cells and a cell sorting by a cell antigen selected from the group consisting of CD34, CD117, CD133, CD201, GloboH and combination thereof, and cultured in a medium supplemented with at least one or more steroids and one or more growth factors. The cells of the invention express CD34 and exhibit sphere-like clonogenicity in early passages and express multipotent embryonic stem cells (ESCs) like characteristics.

Abstract: A method comprises forming a plurality of interconnect components over a gate structure, wherein a bottom metal line of the interconnect components is connected to the gate structure through a gate plug, depositing a dielectric layer over a top metal line of the interconnect components, forming an opening in the dielectric layer, depositing a first barrier layer on a bottom and sidewalls of the opening using a non-plasma based deposition process, depositing a second barrier layer over the first barrier layer using a plasma based deposition process and forming a pad in the opening.

Abstract: The invention provides a plurality of embryonic stem cell-like progenitor cells, which are isolated from a human tissue by a systemic screening of human mesenchymal stromal stem/progenitor cells and a cell sorting by a cell antigen selected from the group consisting of CD34, CD117, CD133, CD201, GloboH and combination thereof, and cultured in a medium supplemented with at least one or more steroids and one or more growth factors. The cells of the invention express CD34 and exhibit sphere-like clonogenicity in early passages and express multipotent embryonic stem cells (ESCs) like characteristics.

Abstract: Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

Abstract: A method for forming interconnect structures comprises forming a metal line made of a first conductive material over a substrate, depositing a dielectric layer over the metal line, patterning the dielectric layer to form an opening, depositing a first barrier layer on a bottom and sidewalls of the opening using an atomic layer deposition technique, depositing a second barrier layer over the first barrier layer, wherein the first barrier layer is coupled to ground and forming a pad made of a second conductive material in the opening.

Abstract: A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials.