Patents by Inventor Ming Tsai

Ming Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220248064
    Abstract: A video coder that implements illumination compensation is provided. The video coder receives a first block of pixels in a first video picture to be coded as a current block, wherein the current block is associated with a motion vector that references a second block of pixels in a second video picture as a reference block. The video coder performs inter-prediction for the current block by using the motion vector to generate a set of motion-compensated pixels for the current block. The video coder modifies the set of motion-compensated pixels of the current block by applying a linear model that is computed based on neighboring samples of the reference block and of the current block. The neighboring samples are identified based on a position of the current block within a larger block.
    Type: Application
    Filed: April 19, 2022
    Publication date: August 4, 2022
    Inventors: Chia-Ming TSAI, Chun-Chia CHEN, Chih-Wei HSU, Ching-Yeh CHEN, Tzu-Der CHUANG
  • Publication number: 20220237361
    Abstract: A method includes: receiving a design layout comprising a feature extending in a peripheral region and a central region of the design layout; determining compensation values associated with a pellicle assembly and the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout according to the compensation values. The modifying of the shape of the feature according to the compensation values includes: partitioning the peripheral region into compensation zones, wherein the feature includes first portions disposed within the respective compensation zones and a second portion disposed within the central region; and reducing line widths of the first portions of the feature according to the compensation values associated with the respective compensation zones while keep the second portion of the feature uncompensated.
    Type: Application
    Filed: April 14, 2022
    Publication date: July 28, 2022
    Inventors: CHI-TA LU, CHIA-HUI LIAO, YIHUNG LIN, CHI-MING TSAI
  • Publication number: 20220239931
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream determines a block boundary of the current block and sub-block boundaries inside the current block, wherein the current block is partitioned into a plurality of sub-blocks using sub-block mode prediction. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a current filtered-reconstructed block, wherein said applying the de-blocking process to the current block comprises applying the de-blocking process to the sub-block boundaries inside the current filtered-reconstructed block, and generates a filtered decoded picture including the current filtered-reconstructed block.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Inventors: Chia-Ming TSAI, Chih-Wei HSU, Ching-Yeh CHEN, Tzu-Der CHUANG, Yu-Wen HUANG
  • Publication number: 20220224886
    Abstract: Video processing methods and apparatuses for coding a current block and a adjacent block comprise receiving input data of the current and adjacent blocks in a current picture, determines the current and adjacent blocks are both coded in a BDPCM or RDPCM mode, performing a deblocking filtering operation on an edge between the current and adjacent blocks by de-activating deblocking filtering for a first color component and activating deblocking filtering for a second color component, and encoding or decoding the current and adjacent blocks. Each current pixel in a BDPCM coded block is predicted by one or more neighboring pixels of the current pixel. RDPCM is applied to process quantized residues of a RDPCM coded block according to a prediction direction of the RDPCM coded block.
    Type: Application
    Filed: May 28, 2020
    Publication date: July 14, 2022
    Inventors: Chia-Ming TSAI, Chih-Wei HSU
  • Patent number: 11387168
    Abstract: A semiconductor device includes a first conductive layer, an organic layer and a silicon layer. The first conductive layer includes a first surface. The organic layer is disposed over the first surface of the first conductive layer. The silicon layer is disposed over the organic layer and extended onto and in contact with the first surface of the first conductive layer.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
  • Publication number: 20220216204
    Abstract: The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Inventors: Su-Hao Liu, Yan-Ming Tsai, Chung-Ting Wei, Ziwei Fang, Chih-Wei Chang, Chien-Hao Chen, Huicheng Chang
  • Patent number: 11376491
    Abstract: A claw machine includes a compartment for containing multiple prizes, a crane module movable in the compartment, a chute, a claw module, a turntable, a coin module, a control system, and an operation module including at least one joy stick and at least one button. In operation, the control system actuates the turntable module. A player is allowed to operate the joy stick and the button to move the crane module, to lift and lower the claw module relative to the crane module, to open and close the claw module to fetch a desired one of prizes, and to open the claw module to drop the desired prize onto the turntable module. The turntable module casts the desired prize toward the chute in a centrifugal manner.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: July 5, 2022
    Assignee: Feiloli Electronic Co., Ltd.
    Inventors: Chi-Ming Tsai, I-Chiang Yang
  • Patent number: 11374114
    Abstract: A high-k dielectric layer is formed over a semiconductor substrate having a first trench and a second trench. A barrier layer is formed over the high-k dielectric layer. A work function layer is deposited over the barrier layer, and is patterned and removed from the second trench, exposing the barrier layer at the second trench. A precursor is deposited selectively over the barrier layer in the second trench, and deposited over the work function layer in the first trench. The precursor selectively reacts with the barrier layer to selectively etch the barrier layer, and selectively reacts with the work function layer to selectively etch a top oxidized portion of the work function layer and deposit a protective layer. The reaction products between the precursor and the barrier layer, and the reaction products between the precursor and the work function layer are removed by using an inert gas.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar P. Savant, Tien-Wei Yu, Ke-Chih Liu, Chia-Ming Tsai
  • Publication number: 20220201286
    Abstract: A video processing method for a video encoder or decoder comprises receiving input data of a current block, determining an intra prediction mode and reference samples according to the intra prediction mode, determining an intra reference sample filter from a Gaussian interpolation filter and an alternative interpolation filter for the current block, applying the intra reference sample filter to the reference samples to generate an intra predictor for the current block, and encoding or decoding the current block based on the intra predictor. A determination between the Gaussian and alternative interpolation filters is depending on a comparison of a mode difference value calculated by the intra prediction mode with a size-dependent threshold. The size-dependent threshold is set to be equal to 24 for blocks with block size smaller than or equal to 32 samples according to an embodiment. The alternative interpolation filter may be a DCT-IF interpolation filter.
    Type: Application
    Filed: April 22, 2020
    Publication date: June 23, 2022
    Inventors: Chia-Ming TSAI, Chih-Wei HSU
  • Publication number: 20220181463
    Abstract: A device includes a semiconductor region, an interfacial layer over the semiconductor region, the interfacial layer including a semiconductor oxide, a high-k dielectric layer over the interfacial layer, and an intermixing layer over the high-k dielectric layer. The intermixing layer includes oxygen, a metal in the high-k dielectric layer, and an additional metal. A work-function layer is over the intermixing layer. A filling-metal region is over the work-function layer.
    Type: Application
    Filed: February 25, 2022
    Publication date: June 9, 2022
    Inventors: Shahaji B. More, Chandrashekhar Prakash Savant, Tien-Wei Yu, Chia-Ming Tsai
  • Patent number: 11356699
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. According to one method, a current block is partitioned into a plurality of sub-blocks using SDIP (Short Distance Intra Prediction mod). A first Bs (boundary strength) for an internal block boundary of the plurality of sub-blocks is determined by setting the first Bs to a second Bs of an Intra-coded boundary block of the current block. De-blocking process is applied, using the first Bs, to reconstructed samples across the internal block boundary of the plurality of sub-blocks to generate filtered-reconstructed samples. In another method, the current block is partitioned into two sub-blocks using SBT (sub-block transform) horizontally or vertically and the first Bs (boundary strength) is determined for an internal block boundary between the two sub-blocks by setting the first Bs to a second Bs of a non-zero cbf (coded block flag) block of the two sub-blocks in step.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 7, 2022
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen
  • Publication number: 20220173048
    Abstract: A semiconductor package device includes a flexible carrier, a first chip, a second chip, a first molding layer, a first adhesive layer and a second molding layer. The flexible carrier has a flexible layer and a rigid layer. The flexible layer has a patterned build-up circuit. The rigid layer is connected to a portion surface of the flexible layer. The position that the flexible layer connected to the rigid layer is formed a first carrying part and a second carrying part. The region of the flexible layer between the first carrying part and the second carrying part without the rigid layer is formed as a first flexible part. The first chip is connected to the first carrying part by flip-chip manner and the second chip is connected to the second carrying part by flip-chip manner. The first molding layer covers the first chip and the second molding layer covers the second chip. The first adhesive layer is connected between the first molding layer and the second carrying part.
    Type: Application
    Filed: November 29, 2021
    Publication date: June 2, 2022
    Inventors: Chun-Hsien Yu, Shih-Ping Hsu, Hsien-Ming Tsai
  • Patent number: 11348839
    Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yip Loh, Yan-Ming Tsai, Hung-Hsu Chen, Chih-Wei Chang, Sheng-Hsuan Lin
  • Publication number: 20220163643
    Abstract: A LiDAR and a method of a fast photon-count integration for a LiDAR are disclosed. The proposed method, wherein the LiDAR includes a laser, includes: providing a target and the LiDAR; causing the laser to fire a laser pulse towards the target according to a random mechanism; and causing an interval between two adjacent laser pulses to be less than a time that the laser spent for a round trip of maximum unambiguous range to speed up a detection and a ranging of the target.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 26, 2022
    Inventors: Tzu-Hsien Sang, Chia-Ming Tsai, Yung-Chien Liu, Ningkai Yang, Ting-Yuan Wang
  • Patent number: 11343541
    Abstract: A video coder that implements illumination compensation is provided. The video coder receives a first block of pixels in a first video picture to be coded as a current block, wherein the current block is associated with a motion vector that references a second block of pixels in a second video picture as a reference block. The video coder performs inter-prediction for the current block by using the motion vector to generate a set of motion-compensated pixels for the current block. The video coder modifies the set of motion-compensated pixels of the current block by applying a linear model that is computed based on neighboring samples of the reference block and of the current block. The neighboring samples are identified based on a position of the current block within a larger block.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 24, 2022
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang
  • Patent number: 11342434
    Abstract: A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chandrashekhar Prakash Savant, Tien-Wei Yu, Chia-Ming Tsai
  • Patent number: 11335774
    Abstract: A device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including NiSi2, a second silicide region on the first silicide region, the second silicide region including TiSix, and a conductive material on the second silicide region.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yan-Ming Tsai, Chih-Wei Chang, Ming-Hsing Tsai, Sheng-Hsuan Lin, Hung-Hsu Chen, Wei-Yip Loh
  • Patent number: 11330277
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. According to one method, if a CU is partitioned into multiple sub-CUs, the de-blocking process is also applied to the sub-block boundaries inside the current filtered-reconstructed block. According to another method, if first reference samples used for the de-blocking process of a first boundary are to be modified by the de-blocking process of a second boundary, the first reference samples are replaced by padding samples that are not to be modified by the de-blocking process of the second boundary. According to yet another method, the de-blocking process is applied to a reconstructed block corresponding to a current block to result in a current filtered-reconstructed block regardless whether a boundary of the current block corresponds to an 8×8 sample grid boundaries.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 10, 2022
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Publication number: 20220138570
    Abstract: A system performs the operations of a neural network agent and a circuit simulator for analog circuit sizing. The system receives an input indicating a specification of an analog circuit and design parameters. The system iteratively searches a design space until a circuit size is found to satisfy the specification and the design parameters. In each iteration, the neural network agent calculates measurement estimates for random sample generated in a trust region, which is a portion of the design space. Based on the measurement estimate, the system identifies a candidate size that optimizes a value metric. The circuit simulator receives the candidate size and generates a simulation measurement. The system calculates updates to weights of the neural network agent and the trust region for a next iteration based on, at least in part, the simulation measurement.
    Type: Application
    Filed: October 6, 2021
    Publication date: May 5, 2022
    Inventors: Chia-Yu Tsai, Hung-Hao Shen, Chen-Feng Chiang, Chung-An Wang, Yiju Ting, Chia-Shun Yeh, Chin-Tang Lai, Feng-Ming Tsai, Kai-En Yang
  • Patent number: 11320742
    Abstract: The present disclosure provides a method and a system for generating photomask patterns. The system obtains a design layout image, and generates a hotspot image corresponding to the design layout image based on a hotspot detection model. The system generates two photomask patterns based on the hotspot image. The at least two photomask patterns are transferred onto a semiconductor substrate.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Tung Hu, Kuan-Chi Chen, Ya-Hsuan Wu, Shiuan-Li Lin, Chih-Chung Huang, Chi-Ming Tsai