Patents by Inventor Ming Tsai

Ming Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220130677
    Abstract: The present disclosure describes method to form a semiconductor device with a diffusion barrier layer. The method includes forming a gate dielectric layer on a fin structure, forming a work function stack on the gate dielectric layer, reducing a carbon concentration in the work function stack, forming a barrier layer on the work function stack, and forming a metal layer over the barrier layer. The barrier layer blocks a diffusion of impurities into the work function stack, the gate dielectric layer, and the fin structure.
    Type: Application
    Filed: October 27, 2020
    Publication date: April 28, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar Prakash SAVANT, Tien-Wei Yu, Chia-Ming Tsai
  • Patent number: 11314296
    Abstract: An example computing device may include a housing having an outer panel, the outer panel comprising a first array of openings through the outer panel, an inner panel opposite the outer panel, the inner panel comprising a second array of openings and a third array of openings different than the second array of openings and an actuator to move the inner panel relative to the outer panel between (1) a first position in which the second array of openings are at least partially aligned with the first array of openings and the third array of openings are out of alignment with the first array of openings, and (2) a second position in which the third array of openings are at least partially aligned with the first array of openings and the second array of openings are out of alignment with the first array of openings.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: April 26, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chia-Ming Tsai, Cheng-Han Tsai, John J. Groden, Hui Leng Lim
  • Patent number: 11317021
    Abstract: A display device and a control circuit thereof are provided. The display device includes: a display panel that is foldable and a housing that is foldable and used for supporting the display panel. The display panel has a folding axis and is divided into a first display area and a second display area along the folding axis; the first display area and the second display area partially overlap in a case where the display panel is in a folded state along the folding axis, and the second display area comprises a non-overlapping portion that does not overlap the first display area; and a component is provided at a position of the housing supporting the non-overlapping portion.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: April 26, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wenbo Wang, Pao Ming Tsai
  • Patent number: 11308254
    Abstract: A method, a non-transitory computer-readable storage medium and a system for adjusting a design layout are provided. The method includes: receiving a design layout including a feature in a peripheral region of the design layout; determining a first compensation value associated with the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout by modifying a shape of the feature according to the compensation value.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Ta Lu, Chia-Hui Liao, Yihung Lin, Chi-Ming Tsai
  • Publication number: 20220115521
    Abstract: The present disclosure describes method to form a semiconductor device having a gate dielectric layer with controlled doping and to form multiple devices with different Vt. The method includes forming a gate dielectric layer on a fin structure, forming a buffer layer on the gate dielectric layer, and forming a dopant source layer including a dopant on the buffer layer. The gate dielectric layer includes an interfacial layer on the fin structure and a high-k dielectric layer on the interfacial layer. The method further includes doping a portion of the high-k dielectric layer adjacent to the interfacial layer with the dopant, removing the dopant source layer and the buffer layer, forming a dopant pulling layer on the gate dielectric layer, and tuning the dopant in the gate dielectric layer by the dopant pulling layer.
    Type: Application
    Filed: October 14, 2020
    Publication date: April 14, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming TSAI, Tien-Wei Yu
  • Publication number: 20220113621
    Abstract: Present disclosure provides a mask and a method for fabricating a semiconductor device, the mask includes a target pattern having consecutive edges, a first scattering bar and a second scattering bar extending along a primary direction and adjacent to consecutive edges of the target pattern, wherein the first scattering bar and the second scattering bar partially overlaps in the primary direction, and a connecting segment connecting between a first end of the first scattering bar and a first end of the second scattering bar, wherein the first scattering bar is not parallel to the connecting segment.
    Type: Application
    Filed: December 21, 2021
    Publication date: April 14, 2022
    Inventors: HUANG-MING WU, JIUN-HAO LIN, JIA-GUEI JOU, CHI-TA LU, CHI-MING TSAI
  • Patent number: 11302879
    Abstract: A flexible display substrate and a manufacturing method therefor, and a display apparatus, for relieving the problem that it is difficult to bend the flexible display substrate in a bending region to damage an upper circuit. The flexible display substrate comprises a back film, a first flexible base substrate located above the back film, and a second flexible base substrate located on one side of the first flexible base substrate facing away from the back film. The flexible display substrate has a bending region. An auxiliary layer is further provided between the first flexible base substrate and the second flexible base substrate. At least part of the auxiliary layer in the bending region can be decomposed in a preset condition, wherein the other film layers except the auxiliary layer are maintained at the original status in the preset condition.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: April 12, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Lu Liu, Pao Ming Tsai, Peng Cai, Hong Li, Dejun Bu, Jianwei Li, Liqiang Chen
  • Patent number: 11289482
    Abstract: The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Hao Liu, Yan-Ming Tsai, Chung-Ting Wei, Ziwei Fang, Chih-Wei Chang, Chien-Hao Chen, Huicheng Chang
  • Publication number: 20220094922
    Abstract: Video processing methods and apparatuses in a video encoding or decoding system for processing out-of-bounds nodes in a current picture. An out-of-bounds node is a coding tree node with a block region across a current picture boundary. The video processing method or apparatus determines an inferred splitting type, applies the inferred splitting type to split the out-of-bounds node into child blocks, adaptively splits each child block into one or multiple leaf blocks, and encodes or decodes the leaf blocks in the out-of-bounds node inside the current picture. The inferred splitting type for partitioning out-of-bounds nodes in an inter slice, picture, or tile is the same as the inferred splitting type for partitioning out-of-bounds nodes in an intra slice, picture, or tile.
    Type: Application
    Filed: December 24, 2019
    Publication date: March 24, 2022
    Inventors: Chia-Ming TSAI, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG, Shih-Ta HSIANG
  • Publication number: 20220088472
    Abstract: A claw machine includes a compartment for containing multiple prizes, a crane module movable in the compartment, a chute, a claw module, a turntable, a coin module, a control system, and an operation module including at least one joy stick and at least one button. In operation, the control system actuates the turntable module. A player is allowed to operate the joy stick and the button to move the crane module, to lift and lower the claw module relative to the crane module, to open and close the claw module to fetch a desired one of prizes, and to open the claw module to drop the desired prize onto the turntable module. The turntable module casts the desired prize toward the chute in a centrifugal manner.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Inventors: Chi-Ming Tsai, I-Chiang Yang
  • Publication number: 20220086439
    Abstract: A method and apparatus for block partition are disclosed. If a cross-colour component prediction mode is allowed, the luma block and the chroma block are partitioned into one or more luma leaf blocks and chroma leaf blocks. If a cross-colour component prediction mode is allowed, whether to enable an LM (Linear Model) mode for a target chroma leaf block is determined based on a first split type applied to an ancestor chroma node of the target chroma leaf block and a second split type applied to a corresponding ancestor luma node. According to another method, after the luma block and the chroma block are partitioned using different partition tress, determine whether one or more exception conditions to allow an LM for a target chroma leaf block are satisfied when the chroma partition tree uses a different split type, a different partition direction, or both from the luma partition tree.
    Type: Application
    Filed: December 30, 2019
    Publication date: March 17, 2022
    Inventors: Chia-Ming TSAI, Tzu-Der CHUANG, Chih-Wei HSU, Ching-Yeh CHEN, Zhi-Yi LIN
  • Publication number: 20220084890
    Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 17, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming TSAI, Ming-Te CHEN, Tien-Wei YU
  • Publication number: 20220077347
    Abstract: Disclosed is a multi-quantum well structure including a stress relief layer, an electron-collecting layer disposed on the stress relief layer, and an active layer including a first active layer unit that is disposed on the electron-collecting layer. The first active layer unit includes potential barrier sub-layers and potential well sub-lavers being alternately stacked, in which at least one of the potential barrier sub-layers has a GaN/Alx1Iny1Ga(1-x1-y1)N stack, where 0<x1?1 and 0?y1<1. An LED device including the multi-quantum well structure is also disclosed.
    Type: Application
    Filed: November 17, 2021
    Publication date: March 10, 2022
    Inventors: HAN JIANG, YUNG-LING LAN, WEN-PIN HUANG, CHANGWEI SONG, LI-CHENG HUANG, FEILIN XUN, CHAN-CHAN LING, CHI-MING TSAI, CHIA-HUNG CHANG
  • Patent number: 11270547
    Abstract: A contactless game controller includes a direction panel, at least one direction module, a button-simulating panel and at least one button-simulating panel. The direction panel is supported on the game machine and includes at least one direction-indicating window. The direction module is located under the direction panel corresponding to the direction-indicating window and electrically connected to the control box. The button-simulating panel is supported on the game machine and includes at least one button-simulating window. The button-simulating module is located under the button-simulating panel corresponding to the button-simulating window and electrically connected to the control box.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: March 8, 2022
    Assignee: Feiloli Electronic Co., Ltd.
    Inventors: Chi-Ming Tsai, I-Chiang Yang
  • Patent number: 11272182
    Abstract: A method and apparatus for video coding using block partition are disclosed. According to the present invention, a partition structure corresponding to recursively partitioning a current block into smaller TU (transform unit) blocks until the partition structure reaches a maximum allowed split depth or until a block size of at least one of smaller TU blocks is a supported core transform size, where the current block is partitioned into final smaller TU blocks according to the partition structure. A transform coding process is applied to the current block according to the partition structure, where the transform coding process is skipped for at least one of the final smaller TU blocks. A flag can be signalled for the current block to indicate whether the current block is allowed to skip the transform coding process for said at least one of the final smaller TU blocks.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: March 8, 2022
    Assignee: MEDIATEK INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Shih-Ta Hsiang, Yu-Wen Huang, Zhi-Yi Lin
  • Patent number: 11264478
    Abstract: A device includes a semiconductor region, an interfacial layer over the semiconductor region, the interfacial layer including a semiconductor oxide, a high-k dielectric layer over the interfacial layer, and an intermixing layer over the high-k dielectric layer. The intermixing layer includes oxygen, a metal in the high-k dielectric layer, and an additional metal. A work-function layer is over the intermixing layer. A filling-metal region is over the work-function layer.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Chandrashekhar Prakash Savant, Tien-Wei Yu, Chia-Ming Tsai
  • Publication number: 20220059684
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 24, 2022
    Inventors: Chandrashekhar Prakash SAVANT, Kin Shun CHONG, Tien-Wei YU, Chia-Ming TSAI, Ming-Te CHEN
  • Publication number: 20220046239
    Abstract: Video processing methods comprise receiving input data of a current block, checking whether the current block is a root block by considering one or more predefined criteria, applying a mode constraint, a chroma split constraint, or both the mode and chroma split constraints to the current block if the current block is set to be a root block, and encoding or decoding the current block. The mode constraint restricts all blocks split from the current block to be processed by a same prediction mode and the chroma split constraints prohibits chroma components of the current block to be further partitioned while allowing a luma component of the current block to be partitioned into smaller blocks.
    Type: Application
    Filed: December 10, 2019
    Publication date: February 10, 2022
    Inventors: Zhi-Yi LIN, Tzu-Der CHUANG, Ching-Yeh CHEN, Chia-Ming TSAI
  • Publication number: 20220034659
    Abstract: A microelectromechanical system (MEMS) gyroscope includes a driving mass and a driving circuit that operates to drive the driving mass in a mechanical oscillation at a resonant drive frequency. An oscillator generates a system clock that is independent of and asynchronous to the resonant drive frequency. A clock generator circuit outputs a first clock and a second clock that are derived from the system clock. The drive loop of the driving circuit including an analog-to-digital converter (ADC) circuit that is clocked by the first clock and a digital signal processing (DSP) circuit that is clocked by the second clock.
    Type: Application
    Filed: October 19, 2021
    Publication date: February 3, 2022
    Applicant: STMicroelectronics, Inc.
    Inventors: Deyou FANG, Chao-Ming TSAI, Milad ALWARDI, Yamu HU, David MCCLURE
  • Publication number: 20220027359
    Abstract: The disclosed embodiments provide a system for performing online hyperparameter tuning in distributed machine learning. During operation, the system uses input data for a first set of versions of a statistical model for a set of entities to calculate a batch of performance metrics for the first set of versions. Next, the system applies an optimization technique to the batch to produce updates to a set of hyperparameters for the statistical model. The system then uses the updates to modulate the execution of a second set of versions of the statistical model for the set of entities. When a new entity is added to the set of entities, the system updates the set of hyperparameters with a new dimension for the new entity.
    Type: Application
    Filed: October 4, 2021
    Publication date: January 27, 2022
    Inventors: Ian B. Wood, Xu Miao, Chang-Ming Tsai, Joel D. Young