Abstract: A semiconductor structure includes a conductive line, a pad layer, and a barrier layer. The conductive line is embedded in a multi-level interconnect structure. The pad layer is over the conductive line. The barrier layer is between the conductive line and the pad layer. The pad layer is electrically connected to the conductive line through the barrier layer, and the barrier layer includes a first poly-crystalline layer and a second poly-crystalline layer. A boundary is between the first poly-crystalline layer and the second poly-crystalline layer.

Abstract: A method of generating knowledge graph, performed by a processing device, includes: obtaining a knowledge document, performing word segmentation and part-of-speech tagging on the knowledge document to generate a number of tagged words, obtaining a number of sentences from the tagged words according to a default sentence pattern, wherein each of the sentences includes a subject, an adverb, a verb and an object, and the adverb corresponding to an adverb type, for each of the sentences, performing: using the subject as a first entity of a triple, using the object as a second entity of the triple, and using the adverb type and the verb as a relation in the triple, and forming a knowledge graph using the triple corresponding to each of the sentences.

Abstract: An intraocular pressure inspection device includes an intraocular pressure detection unit, a high-precision positioning system and a wide-area positioning system, wherein according to the position of the intraocular pressure detection unit, a set of high-precision coordinates output by the high-precision positioning system and a set of wide-area coordinates output by the wide-area positioning system are integrated in appropriate weights to obtain a set of more precise integrated coordinate. The above-mentioned intraocular pressure inspection device can prevent the intraocular pressure detection unit from failing to operate once it is not in the working area of the high-precision positioning system.

Abstract: In some embodiments, the present disclosure relates to an integrated chip fabrication device. The device includes a stealth laser apparatus arranged over a chuck configured to hold a substrate. An infrared camera is arranged over the chuck and configured to detect an alignment mark below the substrate. The alignment mark is used to align the stealth laser apparatus over the chuck. Control circuitry is configured to operate the stealth laser apparatus to form a stealth damage region at a location within the substrate that is determined based upon the alignment mark. The stealth damage region separates an inner region of the substrate from an outer region of the substrate.

Abstract: A wireless device with a slot antenna includes one or more heat spreaders, a PCB with vias to allow current to flow through the PCB, various components disposed on the PCB, and a slot antenna compliment. By layering the components, e.g., heat spreaders, PCB, slot antenna compliment, etc. one or more slot antennas are formed from these components as to integrate the slot antennas into the existing structure. The formed slot antenna is a spiraled shape as to reduce the overall footprint of the slot antenna while keeping the required quarter-wavelength total effective length of an open-slot antenna. The formed slot antenna is wide enough to allow the antenna to accommodate a wide bandwidth and may include a plurality of steps to further allow for tuning of the length of the slot antenna. The wireless device can further include a housing enclosing the internal components.

Abstract: A bond pad connector to be disposed on a stretchable substrate and adapted to secure an electronic component thereon. The bond pad connector includes two spaced apart bond pads that are adapted to be disposed on the stretchable substrate to face each other. Each of the two bond pads is adapted to be connected to a respective conductive trace and includes: a stress relieve component that is adapted to be connected to the conductive trace, the stress relieve component being formed with a central hole; and an extension component extending from the stress relieve component and opposite to the conductive trace. The electronic component is secured onto the bond pad connector by attaching the electronic component to, for each of the bond pads, at least a part of the extension component.

Abstract: A method for forming a semiconductor structure includes the steps of forming a stacked structure on a substrate, forming an insulating layer on the stacked structure, forming a passivation layer on the insulating layer, performing an etching process to form an opening through the passivation layer and the insulating layer to expose a portion of the stacked structure and an extending portion of the insulating layer, and forming a contact structure filling the opening and directly contacting the stacked structure, wherein the extending portion of the insulating layer is adjacent to a surface of the stacked structure directly contacting the contact structure.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Abstract: In some embodiments, the present disclosure relates to a method that includes aligning a stealth laser apparatus over a wafer using an infrared camera coupled to the stealth laser apparatus. The stealth laser apparatus is used to form a stealth damage region within the wafer that is continuously connected around the wafer and separates an inner region from an outer region of the wafer. The stealth damage region is also arranged at a first distance from an edge of the wafer and extends from a first depth to a second depth beneath a top surface of the wafer. Further, the method includes forming a groove in the wafer to separate the outer region from the inner region of the wafer. The outer region of the wafer is removed using a blade, and a top portion of the inner region of the wafer is removed using a grinding apparatus.

Abstract: A method of building a knowledge graph, performed by a processing device, includes: classifying news articles to a main event associated with sub events, using the main event as a first node of the knowledge graph, using the sub events as second nodes of the knowledge graph respectively, connecting the second nodes to the first node, extracting event summaries from the news articles respectively according to a template, using the event summaries as third nodes of the knowledge graph respectively, and connecting each of the third nodes to one of the second nodes according to association between the event summaries and the sub events, extracting commenter identities from the event summaries, and using the commenter identities as fourth nodes of the knowledge graph, and connecting each of the fourth nodes to one of the third nodes.

Abstract: A method for regenerating a secondary battery is disclosed and includes a discharge step before drilling, wherein the secondary battery is discharged so that no current is generated between two electrodes; a drilling step, wherein the secondary battery is drilled from an electrode terminal towards an internal direction of the secondary battery until passing through a spacer inside the secondary battery to form a drilled hole in the spacer; a solution replenishing step, wherein a solution injection needle is used to pass through the drilled hole to inject internally to the secondary battery with a supplemental electrolyte solution and the injection pressure of the supplemental electrolyte solution injected is greater than the internal pressure inside the secondary battery; and a sealing step, wherein the solution injection needle is withdrawn from the drilled hole and a sealant is applied to the drilled hole until the sealant is cured and solidified.

Abstract: In some embodiments, the present disclosure relates to method for trimming and cleaning an edge of a wafer. The method includes trimming an outer edge portion of the wafer with a blade along a continuously connected trim path to define a new sidewall of the wafer. The trimming produces contaminant particles on the wafer. Further, the method includes applying deionized water to the new sidewall of the wafer with water nozzles to remove the contaminant particles. The method also includes applying pressurized gas to the wafer at a first top surface area of the wafer with an air jet nozzle. The pressurized gas is directed outward from a center of the wafer to remove remaining contaminant particles. The applying of deionized water and the applying of pressurized gas are performed in a same chamber as the trimming.

Abstract: A rotor system for generating kinetic energy by expanding an unbalanced torque by means of material energy is provided. The rotor has a horizontal rotating shaft and a plurality of sets of radiating members, and each of radiating members combines with a swingable mass and a slidable member that are combined with each other by a transmission system. The slidable member has two containers, each with an opening for holding the substances in the opposite direction, and after the substances are injected into a specific orientation, due to the total weight being greater than the swingable mass that plus the inclination and gravity, which causes the swingable mass to be swung at one hundred and eighty degrees. Therefore, an outer ring system and an inner ring system both generate the torsion toward the running direction so that the entire rotor system generates good operating kinetic energy.

Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a redistribution layer, a die, a heat spreader, a thermal interface material and a molding layer. The die is disposed on the redistribution layer. The heat spreader is disposed on the die. The thermal interface material is applied between the heat spreader and the die. The molding layer is formed on the redistribution layer to enclose the die. The present disclosure further provides a method of manufacturing the above semiconductor package.

Abstract: The present disclosure provides an electronic package. The electronic package includes a substrate, an electronic component, a plurality of conductive elements, a metal sheet and a molding layer. The electronic component is disposed on the substrate and electrically connected to the substrate. The conductive elements are disposed on the substrate and electrically connected with the grounding circuit on the substrate. The metal sheet is disposed above the electronic component and is in electrical contact with the conductive elements. The molding layer is formed between the substrate and the metal sheet to enclose the electronic component and the conductive elements. The present disclosure further provides a method of manufacturing the above electronic package.

Abstract: The wafer thinning method of the present disclosure includes: providing a wafer having a front surface and a back surface opposite to the front surface; grinding the back surface of the wafer with a grinding bit to thin the wafer to a predetermined thickness; dicing the wafer with a dicing blade; ablating the wafer by performing a chemical solution or plasma process on the back surface of the wafer to thin the wafer; and separating the wafer into a plurality of dies.

Abstract: The present disclosure provides an electronic package. The electronic package includes a substrate, an electronic component, a plurality of conductive elements, a metal sheet and a molding layer. The electronic component is disposed on the substrate and electrically connected to the substrate. The conductive elements are disposed on the substrate and electrically connected with the grounding circuit on the substrate. The metal sheet is disposed above the electronic component and is in electrical contact with the conductive elements. The molding layer is formed between the substrate and the metal sheet to enclose the electronic component and the conductive elements. The present disclosure further provides a method of manufacturing the above electronic package.

Abstract: The method of manufacturing a semiconductor package of the present disclosure includes: providing a redistribution layer having opposing first surface and second surface; disposing a die on the first surface of the redistribution layer and electrically connecting the die to the redistribution layer; forming a mask on the second surface of the redistribution layer; performing a chemical or plasma etching process on the second surface of the redistribution layer to expose the conductive traces in the redistribution layer; removing the mask; and forming a plurality of conductive bumps on the second surface of the redistribution layer and electrically connecting the conductive bumps to the exposed conductive traces in the redistribution layer.

Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a redistribution layer, a die, a heat spreader, a thermal interface material and a molding layer. The die is disposed on the redistribution layer. The heat spreader is disposed on the die. The thermal interface material is applied between the heat spreader and the die. The molding layer is formed on the redistribution layer to enclose the die. The present disclosure further provides a method of manufacturing the above semiconductor package.