Abstract: The method of manufacturing a semiconductor package of the present disclosure includes: providing a redistribution layer having opposing first surface and second surface; disposing a die on the first surface of the redistribution layer and electrically connecting the die to the redistribution layer; forming a mask on the second surface of the redistribution layer; performing a chemical or plasma etching process on the second surface of the redistribution layer to expose the conductive traces in the redistribution layer; removing the mask; and forming a plurality of conductive bumps on the second surface of the redistribution layer and electrically connecting the conductive bumps to the exposed conductive traces in the redistribution layer.

Abstract: A wafer carrier assembly includes a wafer carrier and a fluid passage. The wafer carrier comprises a retainer ring confining a wafer accommodation space. The fluid passage is inside the wafer carrier. The fluid passage includes an inlet and at least an outlet to dispense fluid into the wafer accommodation space.

Abstract: A system for distinguishing an individual having an abnormal body temperature includes an interface module receiving a visible light image and a thermal image, a determining module executing an image analysis process on the visible light image to recognize an individual in the visible light image and to determine position data of the individual, and a processing module obtaining a temperature value corresponding to the individual from the thermal image according to the position data. The processing module further determines whether the temperature value falls within a predetermined range of abnormal body temperature, and outputs a warning signal when it is determined that the temperature value falls within the predetermined range of abnormal body temperature.

Abstract: In some embodiments, the present disclosure relates to method for trimming and cleaning an edge of a wafer. The method includes trimming an outer edge portion of the wafer with a blade along a continuously connected trim path to define a new sidewall of the wafer. The trimming produces contaminant particles on the wafer. Further, the method includes applying deionized water to the new sidewall of the wafer with water nozzles to remove the contaminant particles. The method also includes applying pressurized gas to the wafer at a first top surface area of the wafer with an air jet nozzle. The pressurized gas is directed outward from a center of the wafer to remove remaining contaminant particles. The applying of deionized water and the applying of pressurized gas are performed in a same chamber as the trimming.

Abstract: In some embodiments, the present disclosure relates to a wafer trimming and cleaning apparatus, which includes a blade that is configured to trim a damaged edge portion of a wafer, thereby defining a new sidewall of the wafer. The wafer trimming and cleaning apparatus further includes water nozzles and an air jet nozzle. The water nozzles are configured to apply deionized water to the new sidewall of the wafer to remove contaminant particles generated by the blade. The air jet nozzle is configured to apply pressurized gas to a first top surface area of the wafer to remove the contaminant particles generated by the blade. The first top surface area overlies the new sidewall of the wafer.

Abstract: In some embodiments, the present disclosure relates to a method that includes aligning a stealth laser apparatus over a wafer using an infrared camera coupled to the stealth laser apparatus. The stealth laser apparatus is used to form a stealth damage region within the wafer that is continuously connected around the wafer and separates an inner region from an outer region of the wafer. The stealth damage region is also arranged at a first distance from an edge of the wafer and extends from a first depth to a second depth beneath a top surface of the wafer. Further, the method includes forming a groove in the wafer to separate the outer region from the inner region of the wafer. The outer region of the wafer is removed using a blade, and a top portion of the inner region of the wafer is removed using a grinding apparatus.

Abstract: A method for providing a piezoelectric device is described. The method includes providing a first electrode layer on a substrate and coating at least one layer of piezoelectric material. The coating using at least one of clot-die coating, dip coating, aerosol coating and R2R coating such that a layer of the at least one layer of piezoelectric material has a variation in thickness of not more than ten percent. The layer(s) of piezoelectric materials are also heat treated. Multiple layers of piezoelectric material may be slot-die coated and heat treated to provide a multilayer having the desired thickness. A second electrode layer is provided on the layer(s) of piezoelectric material.

Abstract: A rotor system for generating kinetic energy by expanding an unbalanced torque by means of material energy is provided. The rotor has a horizontal rotating shaft and a plurality of sets of radiating members, and each of radiating members combines with a swingable mass and a slidable member that are combined with each other by a transmission system. The slidable member has two containers, each with an opening for holding the substances in the opposite direction, and after the substances are injected into a specific orientation, due to the total weight being greater than the swingable mass that plus the inclination and gravity, which causes the swingable mass to be swung at one hundred and eighty degrees. Therefore, an outer ring system and an inner ring system both generate the torsion toward the running direction so that the entire rotor system generates good operating kinetic energy.

Abstract: A disclosed method for manufacturing a printed circuit board includes creating multiple conductive layers, each including conductive traces for carrying high-speed data signals, and a non-round plated through power via for delivering high current from a switched-mode power source to and between the conductive layers. Creating the power via may include drilling an opening through the multiple conductive layers, the perimeter of which has a flattened oval shape, and plating the walls of the opening to a predetermined plating thickness using a conductive material. The power via may have a lower resistivity than a combined resistivity of multiple round, plated through vias that, together with required spacing between them, have the same footprint as the power via. The space occupied by the power via may be less than a required footprint for multiple round, plated through vias whose combined resistivity equals the resistivity of the power via.

Abstract: In some embodiments, the present disclosure relates to a wafer trimming and cleaning apparatus, which includes a blade that is configured to trim a damaged edge portion of a wafer, thereby defining a new sidewall of the wafer. The wafer trimming and cleaning apparatus further includes water nozzles and an air jet nozzle. The water nozzles are configured to apply deionized water to the new sidewall of the wafer to remove contaminant particles generated by the blade. The air jet nozzle is configured to apply pressurized gas to a first top surface area of the wafer to remove the contaminant particles generated by the blade. The first top surface area overlies the new sidewall of the wafer.

Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a first substrate, a first die, a plurality of first electrical contacts, a first encapsulant, a second substrate, a second die, a third die, a plurality of second electrical contacts, a second encapsulant and an adhesive layer. The first die is disposed on a first surface of the first substrate. The first electrical contacts are disposed on a second surface of the first substrate and are electrically connected to the first die. The first encapsulant is formed on the first surface of the first substrate to enclose the first die. The second and third dies are disposed on a first surface of the second substrate. The second electrical contacts are disposed on a second surface of the second substrate and are electrically connected to the second and third dies. The second encapsulant is formed on the first surface of the second substrate to enclose the second and third dies.

Abstract: A planarization apparatus is provided. The planarization apparatus includes a platen, and a grinding wheel. The platen is configured to support a wafer. The grinding wheel is over the platen and configured to grind the wafer. The grinding wheel includes a base ring, and a plurality of grinding teeth mounted on the base ring. The plurality of grinding teeth includes a plurality of grinding abrasives, and the plurality of grinding abrasives is ball type.

Abstract: An apparatus for chemical mechanical polishing includes a pad conditioner. The pad conditioner includes a first disk having a first surface and a second disk having a second surface. The first surface has a first plurality of abrasives with a first mean size and the second surface has a second plurality of abrasives with a second mean size greater than the first mean size.

Abstract: A sealing gasket with two deformation spaces is configured to be mounted in a cup-shaped structure and has a through bore that opens on the top and bottom sides of the sealing gasket. The sealing gasket is characterized in that: an inner deformation space and an outer deformation space extend downward into the top side of the sealing gasket, the inner deformation space is adjacent to the through bore such that an inner deformable portion is formed between the inner deformation space and the through bore, and the outer deformation space is adjacent to the outer wall of the sealing gasket such that the outer wall forms an outer deformable portion corresponding to the outer deformation space. The two deformation spaces provide the sealing gasket with enhanced deformability to adapt to a through hole whose diameter may vary within engineering tolerances.

Abstract: A testing method includes the following operations: performing a place and route procedure according to a netlist file corresponding to a chip to generate first layout data; determining whether to replace a flip-flop circuit in the chip with a gated flip-flop circuit according to the first layout data to generate second layout data; and running a test on the chip according to the second layout data.

Abstract: A testing method includes the following operations: performing a place and route procedure according to a netlist file corresponding to a chip, in order to generate first layout data; determining whether to replace a flip-flop circuit in the chip with a gated flip-flop circuit according to the first layout data, in order to generate second layout data; and running a test on the chip according to the second layout data.

Abstract: A wafer carrier assembly includes a wafer carrier and a fluid passage. The wafer carrier comprises a retainer ring confining a wafer accommodation space. The fluid passage is inside the wafer carrier. The fluid passage includes an inlet and at least an outlet to dispense fluid into the wafer accommodation space.

Abstract: A method of monitoring a processing system for processing a substrate is provided. The method includes the following steps: acquiring data from the processing system for a plurality of parameters, the data including a plurality of data values; grouping the parameters into a plurality of sub-groups, each of the sub-groups including a plurality of correlated parameters; constructing a principle components analysis (PCA) model from the data values for the correlated parameters in a first one of the sub-groups, including normalizing the data values in the first one of the sub-groups with a first weighting factor and a second weighting factor, wherein the first weighting factor is different from the second weighting factor; and determining a statistical quantity using the PCA model.

Abstract: The present invention discloses a method and apparatus for routing a message. Specifically, the method for example may comprise: receiving a message lacking a recipient address; searching for at least one recipient address based on a topic associated with the message; and sending the message to the at least one recipient address. The technology according to the example embodiments of the present invention provides a novel technology for routing a message to a recipient based on a topic associated with the message.

Abstract: A lithium ion secondary battery includes a battery casing, an electrode set reeled inside the battery casing and having a positive electrode and a negative electrode, a positive electrode terminal exposed from a top end of the battery casing and connected to the positive electrode and a negative electrode terminal located at a bottom end of the battery casing and connected to the negative electrode, the lithium ion secondary battery further includes: a super capacitor substrate, disposed in the battery casing and extended between two distal ends of the battery casing, and includes a substrate, a first copper foil connected to the positive electrode terminal, a second copper foil connected to the negative electrode terminal, and at least one capacitor connected to the first copper foil and the second copper foil; and an electrolyte, suitable to be applied in the lithium ion secondary battery.