Abstract: A memory apparatus includes memory cells configured to store a threshold voltage and disposed in memory holes each defining a channel. The memory apparatus also includes a control means configured to apply a first erase voltage to the channel of each of the memory holes including the memory cells in a first loop of an erase operation. The control means verifies the threshold voltage of the memory cells being erased using a target erase verify level voltage and at least one high erase verify level voltage higher than the target erase verify level voltage. The control means slows erasing of ones of the memory cells in a second loop of the erase operation in response to the threshold voltage of the ones of the memory cells being erased being greater than the target erase verify level voltage and less than the at least one high erase verify level voltage.

Abstract: Technology is disclosed herein for programing memory cells with a post-program erase. In an aspect, the post-program erase includes a bit-level erase that only erases memory cells that are to remain in an erased state after the program operation. Memory cells that are to remain in programmed states may be inhibited from erase during the post-program erase. In an aspect, the post-program erase does not have an erase verify, which saves time and/or power. In an aspect, the post-program erase includes applying a single erase pulse, which saves time and/or power. In an aspect, the duration of the post-program erase pulse is shorter than an erase pulse used prior to programming, which saves time and/or power.

Abstract: Technology for retrying failed reads of non-volatile memory such as NAND. The memory system retries the failed read using one or more different read techniques than the failed read until the read is successful. The memory system may use different read reference voltages for read retries than the read reference voltages used in the failed read. After a successful read retry the memory system determines whether the original read failed due to an inherent reliability issue or a physical defect. If there is a physical defect the memory cells may be retired. In an embodiment, the entire block of memory cells having the physical defect is retired. However, if the read failed due to an inherent reliability issue then the memory cells may continue to be used.

Abstract: Systems and methods are provided for monitoring properties of a web during a roll-to-roll manufacturing process. The methods may include moving the web past a first roller such that the web contacts the first roller, wherein the first roller includes a first contact strip formed of an electrically conductive material and extends circumferentially about the first roller, applying a voltage to the first contact strip while moving the web past the first roller, such that the voltage conducts through the web to a second contact strip, measuring the voltage received by the second contact strip, determining local resistance values relative to positions of the web based on the difference in the voltage applied to the first contact strip and the voltage received by the second contact strip, and determining at least one property of the web relative to the positions of the web based on the local resistance values.

Abstract: A nonvolatile storage apparatus includes nonvolatile memory cells, bit lines connected to the nonvolatile memory cells and one or more control circuits connected to the nonvolatile memory cells and the bit lines. The one or more control circuits are configured to store weights in the nonvolatile memory cells. Each individual weight is stored by a group of two or more nonvolatile memory cells.

Abstract: A non-volatile memory is divided into multiple zones of non-volatile memory cells. During a sensing operation that includes concurrently sensing total output current from a bit line while the bit line is concurrently receiving output current from multiple non-volatile memory cells that are in different zones, different voltages are applied to selected word lines in different zones based on how far a respective zone is from the bit line driver.

Abstract: Provided is a display panel, including: a substrate; an auxiliary electrode on a side of the substrate; an insulating layer on a side, distal from the substrate, of the auxiliary electrode and a first via running through the insulating layer, the first via exposing the auxiliary electrode and being in an undercut shape; an anode layer on a side, distal from the substrate, of the insulating layer; a light emitting layer on a side, distal from the substrate, of the anode layer, the light emitting layer being broken at an opening in a side, distal from the substrate, of the first via into a first part and a second part; and a cathode layer on a side, distal from the substrate, of the light emitting layer, the cathode layer being coupled with the auxiliary electrode along a side wall of the first part of the light emitting layer.

Abstract: The present invention relates to Compounds of Formula I: and pharmaceutically acceptable salts or prodrug thereof, wherein R1, R2, R3, R4 and A are as defined herein. The present invention also relates to compositions comprising at least one compound of Formula I, and methods of using the compounds of Formula I for treating or preventing HIV infection in a subject.

Abstract: A non-volatile memory attempts to read a data set from a plurality of non-volatile memory cells in multiple threshold voltages distributions and determines that the data set was not read successfully due to there being too many errors in the data read. In response to determining that the data set was not read successfully, the system identifies memory cells storing error bits that are in upper tails and lower tails of the threshold voltages distributions. To reduce the number of errors, memory cells storing error bits that are in upper tails have their threshold voltages reduced by bit level erase and memory cells storing error bits that are in lower tails their threshold voltages increased to move the memory cells closer to the center of their respective threshold voltages distributions by bit level program.

Abstract: The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory cells of a selected word line of the plurality of word lines are programmed to contain data. The memory device also includes circuitry that is configured to perform a read operation on the memory cells of the selected word line using a reference voltage. In response to the read operation passing, the circuitry is configured to end the read operation. In response to the read operation failing, the circuitry is configured to perform an in-place erase operation on only the selected word line to lower threshold voltages of a plurality of selected memory cells of the selected word line while a plurality of unselected memory cells of the selected word line do not have their threshold voltages lowered.

Abstract: A memory apparatus includes memory cells connected to word lines and configured to store a threshold voltage corresponding to data states. The memory cells are disposed in memory holes coupled to bit lines. A control means applies program pulses to selected ones of the word lines. The control means determines when the threshold voltage of each of the memory cells exceeds a lower verify level of one of the data states targeted and maintains a respective count of a number of the program pulses subsequently applied thereto before reaching a lockout state. Each of the program pulses is divided into phases. The control means sets a voltage of one of the bit lines coupled to each of the memory cells at a stepped up level as a function of the respective count and according to each of the phases in which the voltage is set to the stepped up level.

Abstract: A memory apparatus is provided and includes memory cells connected to word lines and coupled to bit lines and configured to retain a threshold voltage corresponding to data states. A control means determines ones of the data states for a first set of the memory cells connected to a selected word line and for a second set of the memory cells connected to at least one neighboring word line. The control means determines which of a plurality of state groups the memory cells of the first and second sets belong according to the data states determined. The control means determines which one of a plurality of bit line voltage biases to be applied to the bit lines coupled to the memory cells of the first set during a verify operation based on a comparison of state groups of the memory cells of the first set and the second set.

Abstract: Disclosed herein is a copolymer, including (A) allyloxycarbonyl substituted benzopinacol monomer of formula (I) and (B) at least one ethylenically unsaturated monomer, in copolymerized form. Also disclosed herein is a use of the copolymer as a radical polymerization initiator. Further disclosed herein is the allyloxycarbonyl substituted benzopinacol monomer of formula (I).

Abstract: Predictive block health assessment of a non-volatile memory can be performed by storing a pre-trained neural network for this purpose on the memory device itself. As operational errors occur during operation of the memory device, this defect data is saved by the non-volatile memory and used as input data for the neural network to identify and retire potential bad blocks before data loss occurs.

Abstract: A memory apparatus includes drain-side select gate transistors for coupling to a drain-side of memory holes of memory cells and configured to retain a drain-side transistor threshold voltage. The memory apparatus also includes source-side select gate transistors for coupling to a source-side of each of the memory holes and configured to retain a source-side transistor threshold voltage. A control means pre-reads the drain-side transistor threshold voltage of the drain-side select gate transistors and the source-side transistor threshold voltage of source-side select gate transistors of the memory holes having the memory cells being erased in an erase operation. The control means adjusts at least one of a drain-side select gate voltage applied to the drain-side select gate transistors and a source-side select gate voltage applied to the source-side select gate transistors based on at least one of the pre-read of the drain-side transistor threshold voltage and the source-side transistor threshold voltage.

Abstract: A non-volatile storage apparatus comprises a non-volatile memory divided into blocks, with each block divided into regions. Each region of a same block includes a plurality of non-volatile memory cells controlled by a separate drain side (or different type of) select line for the region such that different regions of a same block are controlled by different drain side (or different type of) select lines. The non-volatile storage apparatus is configured to concurrently program memory cells in multiple regions.

Abstract: In response to determining that a data set was not read successfully, the system identifies memory cells storing error bits that are in upper tails and lower tails of the threshold voltages distributions. To reduce the number of errors, memory cells storing error bits that are in upper tails have their threshold voltages reduced by bit level erase and memory cells storing error bits that are in lower tails have their threshold voltages increased by bit level program. The identification of which memory cells with error bits are in upper tails and lower tails can be determined on the memory die using a series of latch based operations.

Abstract: A memory device includes a plurality of memory cells each configured to be programmed to a plurality of memory states and control circuitry configured to perform a programming operation to program the plurality of memory cells to respective memory states of the plurality of memory states. To perform the programming operation, the control circuity is configured to supply at least one programming pulse to the plurality of memory cells to program each of the memory cells of the plurality of memory cells to one of the plurality of memory states, and, subsequent to supplying the at least one programming pulse to program each of the plurality memory cells, perform a soft erase operation on selected memory cells of the plurality of memory cells.