Abstract: A display substrate and a display device. The display substrate includes an active layer, a gate insulating pattern, a metal conductive layer and a conductive structure, the gate insulating pattern includes a first opening, the drain electrode includes a main body part and an extension part extending into the first opening, the extension part is electrically connected with the active layer exposed by the first opening, the conductive structure is overlapped with the extension part, the conductive structure includes a first end part close to the drain electrode and a second end part close to the gate electrode and a middle part located between the first end part and the second end part, the first end part is overlapped with the extension part, the second end part is overlapped with the active layer, and the middle part is at least partially overlapped with the active layer.

Abstract: The present invention provides an ionizable lipid compound, which can target spleen for delivery of biological macromolecules including nucleic acid drugs or nucleic acid vaccines with high efficiency. The present invention also relates to a lipid nanoparticle (LNP) comprising the ionizable lipid compound and an active molecule, and a pharmaceutical composition comprising the lipid nanoparticle.

Abstract: A circuit breaker includes opposing first and second ends. Between the ends are first and second sets of moving and fixed contacts, and first and second arc extinguishing chambers each having a front side close to and a rear side distant from the respective set of moving and fixed contacts. A first air flow channel starts from the rear side of the first arc extinguishing chamber and a second air flow channel starts from the rear side of the second arc extinguishing chamber, with outlets of both channels arranged at the second end. A first arc protection element is arranged at the first end between the rear side of the first arc extinguishing chamber and the outer surface of the first end wall.

Abstract: A thin-film transistor includes an active layer and an electrode layer; the active layer includes a channel region, and first and second regions located at two sides of the channel region in a first direction; the electrode layer includes a gate electrode, a first electrode, and a second electrode; the first region includes a first lap region and a first transmission region, an orthographic projection of the first electrode on the active layer overlaps with the first lap region, the first transmission region includes at least one arc-shaped conductive structure each including a hollow part and a thinning portion at least partially surrounding the hollow part, a thickness of the thinning portion is smaller than a thickness of the active layer in the channel region, and the thinning portion is located at a side of the hollow part close to the edge.

Abstract: Provided are a heating method and a refrigerating and freezing apparatus (200) having a heating unit (100). The heating method includes: controlling a heating unit (100) to operate to heat an object to be processed (150); if a heating suspension condition is met, recording a current heating parameter of the heating unit (100), and controlling the heating unit (100) to stop operating; and if a heating continuation condition is met, controlling the heating unit (100) to continue operating according to the recorded heating parameter. By recording the most recent heating parameter before the heating unit (100) stops heating, heating continues according to the recorded heating parameter after heating is resumed, thereby simplifying a control process, preventing a re-determined heating parameter from causing an object to be processed (150) to be excessively heated, shortening a heating time, and reducing unnecessary energy consumption.

Abstract: A cooking apparatus includes heating devices and heating regions, the heating regions are provided with a heating device, a memory, and a processor. The memory stores a computer program comprising instructions that, when executed by the processor, cause the processor to perform operations including: acquiring image information of food in the cooking apparatus; identifying the image information, and acquiring a food type and a cooking doneness of food corresponding to any one of the heating regions; and controlling, according to the food type and the cooking doneness of the food, operation of the heating device in the corresponding heating region. The cooking apparatus controls the heating of food by cooking region based on the food type and the cooking doneness of the food, thereby achieving uniform food heating, providing a consistent overall cooking doneness, preventing parts of the food from being burned or undercooked, and improving cooking performance.

Abstract: A method for manufacturing an electrode includes feeding an electrode mixture to a first conveyor belt. The electrode mixture includes electrode active materials, conductive carbons and polymeric binders. The first conveyor belt moves the electrode mixture film along a first belt-moving direction. The method further includes transferring the electrode mixture film from the first conveyor belt to a second conveyor belt. The second conveyor belt moves the electrode mixture film along a second longitudinal direction. The first belt-moving direction is oblique angled relative to the second longitudinal direction. The side rollers on the second conveyor fold the electrode mixture film at a certain angle with the support of a pair of guide rollers. The method includes hot pressing the electrode mixture film using at least one hot roller to fiberize the PTFE binder along the second belt-moving direction.

Abstract: Provided in the present disclosure are an array substrate, a manufacturing method therefor, and a display apparatus. The array substrate includes: a substrate structure; an active layer on the substrate structure; a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer being provided with a first through hole exposing a portion of the active layer; a first conductive layer in the first through hole and in contact with the active layer; and a first connection member on a side of the first insulating layer away from the substrate structure, the first connection member being in contact with the first conductive layer, and the first connection member covering a first portion of the first conductive layer and not covering a second portion of the first conductive layer.

Abstract: A display panel and a method for preparing the same, and a display device are provided. The display panel includes a substrate, a plurality of sub-pixel units formed on the substrate, and a plurality of MIMIM dual-resonance structures; each sub-pixel unit includes an oxide TFT; the MIMIM dual-resonance structure includes a first metal layer, a first insulator layer, a light absorbing layer, a second insulator layer, and a second metal layer laminated sequentially in that order in a direction away from the substrate; the light absorbing layer is used to absorb incident blue light; a first spacing area is formed between the blue sub-pixel unit and the sub-pixel unit adjacent thereto; the MIMIM dual-resonance structure is arranged in the first spacing area and is located between the blue sub-pixel unit and the oxide TFT of the sub-pixel unit adjacent thereto.

Abstract: The present disclosure relates to an application of stem cells or transgenic stem cells, and specifically, the stem cells or transgenic stem cells are used for preparing a stem cell gel solution or tissue-engineered cartilage. Finally obtained grafts are capable of expressing active proteins. These proteins induce differentiation of a host's own stem cells into chondrocytes. This process accelerates graft integration with host tissue.

Abstract: A method for manufacturing electrodes for a battery cell includes providing a first free-standing electrode; providing a current collector including holes; providing a second free-standing electrode; and laminating the current collector between the first free-standing electrode and the second free-standing electrode using at least one of heat and pressure and without using a solvent.

Abstract: A non-volatile memory system stores a pre-trained model in non-volatile memory cells. The model was received pre-trained from a source external to the non-volatile memory system. The non-volatile memory system further includes an inference engine circuit that uses the model with one or more metrics gathered during operation of the non-volatile memory system to attempt to predict defects in the non-volatile memory. In some cases, however, a block (or other grouping) of memory cells fails (e.g., a memory operation fails) despite that the inference engine predicted that the block of memory cells would not fail. In response to the prediction being wrong, the non-volatile memory system gathers one or more metrics describing the operation of the non-volatile memory system when the block failed (or metrics describing the operation of the non-volatile memory system when multiple blocks failed) and uses those metrics to update the model.

Abstract: Disclosed are a thin film transistor and preparation method thereof, display substrate and display apparatus. The thin film transistor includes a base substrate, a shielding layer, buffer layer, active layer, gate insulating layer and conductive layer stacked on the base substrate; the conductive layer includes a gate electrode, source electrode and drain electrode; the active layer includes a channel region, source transition region and drain transition region at two sides of the channel region, source connection region and drain connection region; the source transition region and drain transition region each include a first sub-region, second sub-region and third sub-region connected sequentially, first sub-region is located on a side of second sub-region away from the channel region, third sub-region is located on a side of second sub-region close to the channel region, a thickness of second sub-region is k times that of the channel region, k is 0.8 to 1.5.

Abstract: A heating apparatus, comprising a chamber body, a door body, a drawer, an electromagnetic wave generating system, and a slide rail assembly. The slide rail assembly comprises a fixed rail fixedly connected to the chamber body, and a slide portion capable of sliding along the fixed rail and fixedly connected to the drawer. The chamber body and the door body are each provided with an electromagnetic shielding feature. The slide portion is provided with at least one conductive connector. One end of each conductive connector is used to conductively connect to the electromagnetic shielding feature of the door body, and the other end is used to conductively connect to the fixed rail. Each conductive connector is fastened and conductively connected to the electromagnetic shielding feature of the door body by means of a fastener.

Abstract: Technology for retrying failed reads of non-volatile memory such as NAND. The memory system retries the failed read using one or more different read techniques than the failed read until the read is successful. The memory system may use different read reference voltages for read retries than the read reference voltages used in the failed read. After a successful read retry the memory system determines whether the original read failed due to an inherent reliability issue or a physical defect. If there is a physical defect the memory cells may be retired. In an embodiment, the entire block of memory cells having the physical defect is retired. However, if the read failed due to an inherent reliability issue then the memory cells may continue to be used.

Abstract: Technology for compensation for a sub-block mode (SBM) back pattern effect. When in a sub-block mode, the memory system determines a magnitude for a program verify voltage for a selected word line in a selected sub-block in a selected block. The magnitude for the program verify voltage depends on a programmed status of the word lines in one or more unselected sub-blocks in the selected block when the program verify voltage is applied to the selected word line. The memory system may also determine a magnitude for a read reference voltage for the selected word line. The magnitude for the read reference voltage depends on a programmed status of the word lines in the one or more unselected sub-blocks in the selected block when the read reference voltage is applied to the selected word line.

Abstract: A display substrate, manufacturing method thereof, and display device. In the display substrate, a gate insulating pattern is located at a side of an active layer, a metal conductive layer is at least partially located at a side of the gate insulating pattern. The gate insulating pattern includes a first opening, the active layer includes a second opening, an orthographic projection of the second opening on the base substrate is located within an orthographic projection of the first opening on the base substrate, the metal conductive layer includes a main body part and an extension part, the extension part is electrically connected with the active layer exposed by the first opening, and the conductive structure is overlapped with the extension part, and includes a connection part extending to the second opening and electrically connecting the active layer on two sides of the second opening.

Abstract: The present invention provides an ionizable lipid compound, which can target spleen for delivery of biological macromolecules including nucleic acid drugs or nucleic acid vaccines with high efficiency. The present invention also relates to a lipid nanoparticle (LNP) comprising the ionizable lipid compound and an active molecule, and a pharmaceutical composition comprising the lipid nanoparticle.

Abstract: Embodiments disclosed herein are directed to techniques aimed at mitigating erase disturb during a bit-level erase operation. For example, in some embodiments, the method comprises: applying, during a bit-level erase operation for erasing data from a memory cell of a selected wordline and a selected memory string, a first voltage to an unselected wordline; and applying, during the bit-level erase operation, a second voltage to the unselected wordline, where the second voltage is less than the first voltage. Additionally, in some embodiments, the method comprises: performing, in response to receiving an erase command, a pre-charge cycle; and performing, in response to completing the pre-charge cycle, the bit-level erase operation.

Abstract: A display substrate, a display panel and a display apparatus are provided. The display substrate has a display area and a non-display area at the periphery of the display area. The display substrate includes: multiple fanout wiring groups in the non-display area and a common electrode between adjacent fanout wiring groups in the non-display area. At least one fanout wiring group includes multiple fanout wirings. The common electrode includes a boundary wiring and a common wiring group in a region surrounded by the boundary wiring. The common wiring group includes: multiple first common wirings and multiple second common wirings. The first common wirings and the second common wirings intersect to form a grid structure. The extension direction of at least one first common wiring is the same as the extension direction of at least one fanout wiring.