Abstract: A method for simultaneously forming alkali metal layers includes heating a laminate structure including a top layer, a bottom layer, and an alkali metal layer sandwiched between opposing facing surfaces of the top layer and the bottom layer. The laminate structure is heated to a peel temperature to at least partially melt the alkali metal layer and form a volume of molten alkali metal at the location of a peel site within the alkali metal layer. The top layer and the bottom layer apart from each other such that the alkali metal layer splits internally at the location of the peel site and is divided between the top layer and the bottom layer.

Abstract: Technology for handling neighbor plane disturb when programming non-volatile memory such as NAND. A memory system performs single level cell (SLC) programming with multiple program loops with verify. The memory system determines SLC programming speed during the SLC programming. The memory system terminates programming early in a plane having slow SLC programming.

Abstract: A memory apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. The memory cells are disposed in memory holes defining channels. The memory cells form a block including a first sub-block and a second sub-block disposed vertically above the first sub-block. A control means is configured to pre-charge the channels of the memory holes in a pre-charge operation. The control means applies each of a series of programming pulses of a program voltage in a program phase followed by verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines in a verify phase to program and verify the memory cells connected thereto during program loops. The pre-charge operation for the second sub-block occurs during the verify phase of a previously occurring one of the plurality of program loops.

Abstract: A foot assembly for a speaker, the foot assembly may include a first portion having a first face configured to abut a surface external to the speaker, a second portion configured to interface with the first portion to create a hollow interior between the first and second portion, the second portion having a second face opposite the first face of the first portion, wherein the second face abuts the speaker, and a fill portion arranged within the hollow interior between the first and second portion to increase shock absorption and sound quality.

Abstract: The present invention provides an ionizable lipid compound having an optimized carbon chain length and an amine head so that the ionizable lipid compound has increased delivery efficiency for an active molecule including, but not limited to, nucleic acids, proteins, small molecule drugs and the like. The present invention further relates to a lipid nanoparticle (LNP) comprising the ionizable lipid compound and the active molecule, and a pharmaceutical composition comprising the lipid nanoparticle.

Abstract: Embodiments disclosed herein are directed to techniques for a programming sequence that implements a combination of single-level cell program modes. For example, a control circuit may program data in a memory storage area by programming a first set of memory cells in the memory storage area with a first subset of the data using a first program mode, where the first program mode includes performing a plurality of program-verify iterations to establish a baseline program voltage. Further, the control circuit may program a second set of memory cells in the memory storage area with a second subset of the data using a second program mode, the second program mode including performing a single program iteration based on the baseline program voltage.

Abstract: Provided are methods of treating a human lipoprotein metabolism disorder or a cardiovascular disease, comprising administering to a subject in need thereof a lipidoid nanoparticle, comprising a lipid, a CRISPR/Cas9 mRNA, and a single guide RNA (sgRNA).

Abstract: Provided in the present disclosure are an array substrate, a manufacturing method therefor, and a display apparatus. The array substrate includes a substrate structure; an active layer on the substrate structure; a patterned first insulating layer on a side of the active layer away from the substrate structure. The first insulating layer being provided with a first through hole exposing a portion of the active layer; a first conductive layer in the first through hole and in contact with the active layer; and a first connection member on a side of the first insulating layer away from the substrate structure. The first connection member being in contact with the first conductive layer, and the first connection member covering a first portion of the first conductive layer and not covering a second portion of the first conductive layer.

Abstract: A memory apparatus includes memory cells configured to store a threshold voltage and disposed in memory holes each defining a channel. The memory apparatus also includes a control means configured to apply a first erase voltage to the channel of each of the memory holes including the memory cells in a first loop of an erase operation. The control means verifies the threshold voltage of the memory cells being erased using a target erase verify level voltage and at least one high erase verify level voltage higher than the target erase verify level voltage. The control means slows erasing of ones of the memory cells in a second loop of the erase operation in response to the threshold voltage of the ones of the memory cells being erased being greater than the target erase verify level voltage and less than the at least one high erase verify level voltage.

Abstract: Technology is disclosed herein for programing memory cells with a post-program erase. In an aspect, the post-program erase includes a bit-level erase that only erases memory cells that are to remain in an erased state after the program operation. Memory cells that are to remain in programmed states may be inhibited from erase during the post-program erase. In an aspect, the post-program erase does not have an erase verify, which saves time and/or power. In an aspect, the post-program erase includes applying a single erase pulse, which saves time and/or power. In an aspect, the duration of the post-program erase pulse is shorter than an erase pulse used prior to programming, which saves time and/or power.

Abstract: Technology for retrying failed reads of non-volatile memory such as NAND. The memory system retries the failed read using one or more different read techniques than the failed read until the read is successful. The memory system may use different read reference voltages for read retries than the read reference voltages used in the failed read. After a successful read retry the memory system determines whether the original read failed due to an inherent reliability issue or a physical defect. If there is a physical defect the memory cells may be retired. In an embodiment, the entire block of memory cells having the physical defect is retired. However, if the read failed due to an inherent reliability issue then the memory cells may continue to be used.

Abstract: Systems and methods are provided for monitoring properties of a web during a roll-to-roll manufacturing process. The methods may include moving the web past a first roller such that the web contacts the first roller, wherein the first roller includes a first contact strip formed of an electrically conductive material and extends circumferentially about the first roller, applying a voltage to the first contact strip while moving the web past the first roller, such that the voltage conducts through the web to a second contact strip, measuring the voltage received by the second contact strip, determining local resistance values relative to positions of the web based on the difference in the voltage applied to the first contact strip and the voltage received by the second contact strip, and determining at least one property of the web relative to the positions of the web based on the local resistance values.

Abstract: A nonvolatile storage apparatus includes nonvolatile memory cells, bit lines connected to the nonvolatile memory cells and one or more control circuits connected to the nonvolatile memory cells and the bit lines. The one or more control circuits are configured to store weights in the nonvolatile memory cells. Each individual weight is stored by a group of two or more nonvolatile memory cells.

Abstract: A non-volatile memory is divided into multiple zones of non-volatile memory cells. During a sensing operation that includes concurrently sensing total output current from a bit line while the bit line is concurrently receiving output current from multiple non-volatile memory cells that are in different zones, different voltages are applied to selected word lines in different zones based on how far a respective zone is from the bit line driver.

Abstract: Provided is a display panel, including: a substrate; an auxiliary electrode on a side of the substrate; an insulating layer on a side, distal from the substrate, of the auxiliary electrode and a first via running through the insulating layer, the first via exposing the auxiliary electrode and being in an undercut shape; an anode layer on a side, distal from the substrate, of the insulating layer; a light emitting layer on a side, distal from the substrate, of the anode layer, the light emitting layer being broken at an opening in a side, distal from the substrate, of the first via into a first part and a second part; and a cathode layer on a side, distal from the substrate, of the light emitting layer, the cathode layer being coupled with the auxiliary electrode along a side wall of the first part of the light emitting layer.

Abstract: The present invention relates to Compounds of Formula I: and pharmaceutically acceptable salts or prodrug thereof, wherein R1, R2, R3, R4 and A are as defined herein. The present invention also relates to compositions comprising at least one compound of Formula I, and methods of using the compounds of Formula I for treating or preventing HIV infection in a subject.

Abstract: A non-volatile memory attempts to read a data set from a plurality of non-volatile memory cells in multiple threshold voltages distributions and determines that the data set was not read successfully due to there being too many errors in the data read. In response to determining that the data set was not read successfully, the system identifies memory cells storing error bits that are in upper tails and lower tails of the threshold voltages distributions. To reduce the number of errors, memory cells storing error bits that are in upper tails have their threshold voltages reduced by bit level erase and memory cells storing error bits that are in lower tails their threshold voltages increased to move the memory cells closer to the center of their respective threshold voltages distributions by bit level program.

Abstract: The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory cells of a selected word line of the plurality of word lines are programmed to contain data. The memory device also includes circuitry that is configured to perform a read operation on the memory cells of the selected word line using a reference voltage. In response to the read operation passing, the circuitry is configured to end the read operation. In response to the read operation failing, the circuitry is configured to perform an in-place erase operation on only the selected word line to lower threshold voltages of a plurality of selected memory cells of the selected word line while a plurality of unselected memory cells of the selected word line do not have their threshold voltages lowered.