Abstract: A wire module is disclosed, which includes a wire group and a wire-distributing device. The wire group has a plurality of wires. The wire-distributing device includes a first wire-distributing module and a second wire-distributing module. The first wire-distributing module has a first wire-distributing member and a first sectional surface. The first sectional surface is located on the surface of one end of the first wire-distributing member, and the first part of the plurality of wires is positioned side by side on the first wire-distributing member. The second wire-distributing module has similar structures and configurations to the first wire-distributing module, wherein the first wire-distributing module is stacked on the second wire-distributing module, and the first sectional surface and the second sectional surface are correspondingly located on the same side.

Abstract: A heat dissipation structure includes a heat dissipation base, at least one heat pipe, and a first heat dissipation contact material and a second heat dissipation contact material that are different from one another. The heat dissipation base has a first and a second heat dissipation surface opposite to each other. At least one recessed trough is concavely formed on the first heat dissipation surface. The at least one heat pipe is located in the at least one recessed trough. The first and the second heat dissipation contact material are filled in the at least one recessed trough. At least one cooling fin is joined to the second heat dissipation surface of the heat dissipation base, and at least one internal coolant passage is defined between the heat dissipation base and the at least one cooling fin.

Abstract: An IC includes a first standard cell (SC1) having a first circuit area (CA1) and a first transition area (TA1) placed on an edge of the CA1; and a SC2 having a CA2 and a TA2 placed on an edge of CA2?. CA1 includes a first and a second active region (AR1 and AR2) longitudinally oriented along a first direction (D1), and a first gate stack (G1) along a D2-D1 and extending over AR1 and AR2. G1 includes a first gate segment (GS1) contacting AR1 and a GS2 contacting AR2. GS1 and GS2 are different in composition. GS1 and GS2 are associated with a pFET and a nFET, respectively. TA1 includes a G2 longitudinally oriented along D2 and spans between opposite cell edges of the SC1. G2 is a lengthwise uniform gate stack. SC2 is placed in abutment with the SC1 such that TA1 and TA2 share a common edge.

Abstract: A drive circuit, a touch drive apparatus, and an electronic device are provided. The circuit comprises a first node, a second node, a ground node, a switch circuit, and an energy storage capacitor. The first node is configured to provide a first positive voltage. The second node is configured to provide a first negative voltage. The switch circuit is configured to control a first terminal of the energy storage capacitor to be selectively connected to the ground node or the drive electrode, and control a second terminal of the energy storage capacitor to be selectively connected to the ground node or the drive electrode. In one phase, the first terminal of the energy storage capacitor receives charges released from the drive electrode. In another phase, the second terminal of the energy storage capacitor charges the drive electrode using stored charges.

Abstract: An optical waveguide, comprising a waveguide substrate (10). A coupling-in area (20) and a coupling-out area (30) are provided on the waveguide substrate (10), the coupling-in area (20) is provided with a coupling-in grating (21), and the coupling-out area (30) comprises a first coupling-out area (31) and a second coupling-out area (32); a first coupling-out grating (41) is provided in the first coupling-out area (31), and a second coupling-out grating (42) is provided in the second coupling-out area (32); the coupling-in grating (21) and the second coupling-out grating (42) are one-dimensional gratings, and the first coupling-out grating (41) is a two-dimensional grating.

Abstract: A projection device includes a shell, an illumination system, an electrical connecting element, a light valve system, and a projection lens. The illumination system is disposed in the shell and provides an illumination beam. The light valve system includes a dustproof module and a light valve module. The dustproof module includes a frame and two transparent plates. An accommodation space is formed by the frame and the two transparent plates. The light valve module includes a light valve and an electrical connecting part. The light valve and the two transparent plates are located on a transmission path of the illumination beam, and the light valve converts the illumination beam into an image beam. One end of the electrical connecting part located in the accommodation space is electrically connected to the light valve, and the other end located outside the accommodation space is detachably electrically connected to the electrical connecting element.

Abstract: A stamp includes a substrate; position limiting structures located on a side of the substrate and spaced apart from each other; and transfer structures, which are located on the side of the substrate where the position limiting structures are located, and are spaced apart from each other. The position limiting structures are in one-to-one correspondence with the transfer structures. Each position limiting structure surrounds a periphery of a corresponding transfer structure, and an orthogonal projection of the position limiting structure on the substrate does not overlap with an orthogonal projection of the corresponding transfer structure on the substrate. A distance between an end surface of an end, which is distal to the substrate, of each transfer structure and the substrate is greater than a distance between an end surface of an end, which is distal to the substrate, of a corresponding position limiting structure and the substrate.

Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers.

Abstract: Disclosed are a wire-guided automatic pay-off device and method. The wire-guided automatic pay-off device is installed on a horizontal directional drilling rig and comprises a conductive ring assembly, a brush assembly, a winding device, a guide device and a guide wire. The conductive ring assembly fixed to a main shaft of a carriage assembly rotates together with the main shaft, the brush assembly fixed to a body of the carriage assembly does not rotate with the main shaft, and a conductive end of the brush assembly is in contact with the conductive ring assembly. The guide wire wound on the winding device has one end connected to the conductive ring assembly and the other end passing through the guide device, penetrating into a central hole in a drill pipe from a rear end of the drill pipe.

Abstract: The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.

Abstract: The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.

Abstract: Methods related to wireless communication systems and uplink (UL) rank adaptation are provided. A user equipment (UE) receives, from a base station (BS), a configuration indicating a resource associated with a plurality of UL reference signal ports. The UE determines, based on at least one of an overheating status, a throughput, or a latency, a quantity of transmission layers for a transmission. The UE transmits, to the BS, an indication of at least one of (1) one or more UL reference signal ports of the plurality of UL reference signal resources associated with the UL reference signal resource based on the quantity of transmission layers, or (2) a number of UL reference signal ports associated with the multi-port UL reference signal resource based on the quantity of transmission layers.

Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

Abstract: Methods, systems, and devices for wireless communications are described. A first user equipment (UE) may receive, from a network entity, a spatial separation indication that indicates, for each of one or more second UEs, a spatial separation between the first UE and each respective second UE. The first UE may forward first data to a selected second UE of the one or more second UEs, where the first data is forwarded as part of an uplink UE aggregation procedure that is based on the spatial separation indication. The first and second UEs may each transmit, to the network entity, a respective shared channel transmission in overlapping or non-overlapping resources that includes respective data, an aggregation flag, and a sequence number, where the aggregation flag and the sequence number are indicative that the first and second data are to be aggregated in a sequence order.

Abstract: An optical communication system and a method of signal transmission are provided. The optical communication system includes an optical fiber, a transmission module, and a reception module. The transmission module includes a first optical circuitry operable to: receive a plurality of input optical signals and data; modulate the plurality of input optical signals in accordance with the data and a polarization state of the plurality of input optical signals to generate a plurality of modulated optical signals; combine the plurality of modulated optical signals to form a combined signal; and relaying the combined optical signal to the optical fiber. The optical fiber transmits the combined optical signal to the reception module for detection.

Abstract: Methods, systems, and devices for wireless communications between a user equipment (UE) and network entity are described. The UE may receive, from the network entity, configuration information enabling the UE to report a padding indication pertaining to padding bits the UE inserts and sends in one or more transmissions. The UE may transmit an uplink message and the padding indication according to the configuration information and based on a quantity of padding included by the UE in the uplink message. In some examples, the UE may receive configuration information enabling the UE to apply a flexible time offset between receipt of an uplink grant and transmission of an uplink message. The UE may receive an uplink grant indicating a time offset range defining valid time durations for the flexible time offset. The UE may transmit the uplink message in accordance with the flexible time offset within the time offset range.

Abstract: Methods, systems, and devices for wireless communications are described. The techniques described herein relate to dynamic logical channel (LCH) prioritization. A user equipment (UE) receives a first downlink message including configuration information for enabling a dynamic LCH prioritization that is associated with a dynamic scheduling of one or more LCHs over one or more carriers. The UE receives a second downlink message indicating a selection of the dynamic LCH prioritization from the configuration information. The UE transmits using the one or more LCHs over the one or more carriers, where the one or more LCHs are multiplexed over the one or more carriers based on the selection of the dynamic LCH prioritization.

Abstract: Methods, systems, and devices for wireless communications are described. The techniques described herein relate to coordinating discontinuous reception (DRX) timers between a user equipment (UE) and a network entity. A UE receives a first downlink message that updates one or more timers associated with triggering a connected mode discontinuous reception (C-DRX) at the UE. The UE transmits a first uplink message prior to an expiration of the one or more timers associated with triggering the C-DRX. The first uplink message indicates whether the UE expects to restart the one or more timers or to enter the C-DRX following transmission of the first uplink message. The UE selects to enter the C-DRX or remain in an awake state following transmission of the first uplink message based on a status of the one or more timers associated with triggering the C-DRX at the UE and the indication of the first uplink message.