Ming Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.
Abstract: A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.
Abstract: A finger protective cap for fitting on an installation part at an end of a connection terminal includes a peripheral wall, an end wall connected to an end of the peripheral wall, and an insertion post located in the inner cavity and connected to the end wall. The peripheral wall and end wall define an inner cavity accommodating the installation part. The insertion post is insertable into an insertion hole on the installation part and interference fit with a hole wall of the insertion hole. The inner cavity has an opening opposite to the end wall to allow the installation part to be inserted into the finger protective cap through the opening.
Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.
Abstract: A communication method includes: generating an extremely high-throughput physical layer protocol data unit (EHT PPDU) that comprises a legacy physical layer preamble and a new physical layer preamble, wherein the legacy physical layer preamble comprises a legacy short training field (L-STF), a legacy long training field (L-LTF), and a legacy signal (L-SIG) field in turn, and wherein a first field of the new physical layer preamble is a repeat of a field in the legacy physical layer preamble and is modulated by binary phase shift keying, BPSK; and sending the PPDU.
Abstract: A method for forming a semiconductor structure is provided. The method includes forming an interconnect structure, and forming a conductive feature electrically connected to the interconnect structure. The method also includes forming a first passivation layer over the interconnect structure and the conductive feature, and etching the first passivation layer to form an opening that exposes the conductive feature. The method further includes performing an electrical test on the conductive feature, filling the opening with an oxide material, and attaching a carrier substrate over the oxide material using a bonding layer.
Abstract: A semiconductor structure includes a first fin and a second fin protruding from a substrate, isolation features over the substrate to separate the first and the second fins, where a top surface of each of the first and the second fins is below a top surface of the isolation features, inner fin spacers disposed along inner sidewalls of the first and the second fins, where the inner fin spacers have a first height measured from a top surface of the isolation features, outer fin spacers disposed along outer sidewalls of the first and the second fins, where the outer fin spacers have a second height measured from the top surface of the isolation features that is less than the first height, and a source/drain (S/D) structure merging the first and the second fins, where the S/D structure includes an air gap having a top portion over the inner fin spacers.
Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.
Abstract: A chemical dispensing system is capable of simultaneously supplying a semiconductor processing chemical for production and testing through the use of independent chemical supply lines, which reduces production downtime of an associated semiconductor process, increases throughput and capability of the semiconductor process, and/or the like. Moreover, the capability to simultaneously supply the semiconductor processing chemical for production and testing allows for an increased quantity of semiconductor processing chemical batches to be tested with minimal impact to production, which increases quality control over the semiconductor processing chemical. In addition, the independent chemical supply lines may be used to supply the semiconductor processing chemical to production while independently filtering semiconductor processing chemical directly from a storage drum through a filtration loop.
Abstract: A connection terminal includes a body part and an installation part. The body part is insertable into a mating terminal for electrical contact with the mating terminal. The installation part is insertable into a finger protective cap for installing the finger protective cap. The installation part is formed on and protrudes from an end face of an end of the body part. A root of the installation part connected to the end face of the body part is formed into an arc-shaped connection part, preventing stress concentration at the root.
Abstract: An anti-fuse array includes first through fourth adjacent anti-fuse bit columns, the anti-fuse bits of the first and second anti-fuse bit columns including portions of active areas of a first active area column, and the anti-fuse bits of the third and fourth anti-fuse bit columns including portions of active areas of a second active area column. Each row of a first set of conductive segment rows includes first and second conductive segments positioned between adjacent active areas of the first active area column and a third conductive segment positioned between adjacent active areas of the second active area column. Each row of a second set of conductive segments alternating with the first set of conductive segment rows includes a fourth conductive segment positioned between adjacent active areas of the first active area column and fifth and sixth conductive segments positioned between adjacent active areas of the second active area column.
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first metal gate stack and a second metal gate stack over the semiconductor substrate. The first metal gate stack and the second metal gate stack are electrically isolated from each other, and the first metal gate stack has a curved edge facing the second metal gate stack. The semiconductor device structure also includes a dielectric layer surrounding the first metal gate stack and the second metal gate stack.
Abstract: In some aspects, a method of wireless communication includes receiving control information by a UE from a base station. The control information indicates one or more first frequency resources of a BWP that are associated with a first communication type and further indicates one or more second frequency resources of the BWP that are associated with a second communication type. The method further includes, based on a first data type of first data corresponding to the first communication type and further based on a second data type of second data corresponding to the second communication type, performing a wireless communication with the base station using the one or more first frequency resources to communicate the first data and using the one or more second frequency resources to communicate the second data.
May 6, 2021
Date of Patent:
November 28, 2023
Ming Yang, Kausik Ray Chaudhuri, Juan Montojo
Abstract: A nanonetwork with controlled chirality prepared via self-assembly of triblock terpolymers, wherein each of the triblock terpolymers includes a first block, a second block and a third block. The first block is connected to the second block, and the third block is connected to the second block. The first block, the second block and the third block are incompatible. The third block has a homochiral characteristic, and a chirality of the nanonetwork with controlled chirality is determined by the homochiral characteristic.
Abstract: A display panel and a light emitting signal generator thereof are provided. The light emitting signal generator includes an output stage circuit, a first control signal generator, a second control signal generator, a switch, and a capacitor. The output stage circuit generates a light emitting signal according to a first control signal and a second control signal. The first control signal generator generates the first control signal at a first control end. The second control signal generator generates the second control signal at a second control end. The switch is coupled between the first control end and the output stage circuit. The first capacitor is coupled to the first control end.
Abstract: Embodiments may include systems, techniques, methods, apparatus and/or device to receive an input selecting one or more areas of a display of the computing device, leaving one or more other areas of the display unselected, and to apply a masking layer to mask either pixels of the one or more selected areas or pixels of the one or more unselected areas to cause the masked pixels to be dimmed, to reduce power consumption by the display. Embodiments may further include where the one or more of the selected areas include a focus area of interest, and to apply the masking layer to mask pixels of the one or more unselected areas to cause the masked pixels to be dimmed. Embodiments may be implemented via software without directly interacting with hardware. Other embodiments may be described or claimed.
Abstract: A mobile terminal and a mobile terminal antenna production method. The mobile terminal uses an insulation film layer on an insulation rear housing as a carrier of a radiating element of an antenna, and the radiating element is located within the entire mobile terminal. A feed and an electric-conductor are disposed on a circuit board, and the electric-conductor is electrically connected to the feed. There is a gap between the radiating element and the electric-conductor, and the electric-conductor indirectly couples the radiating element in a capacitively coupled manner.
Abstract: Provided herein is a next-generation highly-efficient technology that can be used for biocontrol of D. suzukii and/or Aedes aegypti. The composition and technique termed precision guided SIT (pgSIT) functions by exploiting the precision and accuracy of CRISPR to simultaneously disrupt genes essential for either female viability or male fertility. It utilizes a simple breeding scheme requiring two homozygous strains—one expressing Cas9 and the other expressing double guide RNAs (dgRNAs). A single mating between these strains mechanistically results in synchronous RNA-guided dominant biallelic knockouts of both target genes throughout development, resulting in the complete penetrance of desired phenotypes in all progeny. This document provides methods and compositions relating to producing such insect eggs, insects, insect populations and uses thereof in reducing a wild-type insect population, along with methods and materials for producing genetically modified progeny of D. suzukii and/or Aedes aegypti.
July 24, 2020
November 23, 2023
Omar Akbari, Ming Li, Ting Yang, Nikolay Kandul
Abstract: A neural network is used to place macros on a chip canvas in an integrated circuit (IC) design. The macros are first clustered into multiple macro clusters. Then the neural network generates a probability distribution over locations on a grid and aspect ratios of a macro cluster. The grid represents the chip canvas and is formed by rows and columns of grid cells. The macro cluster is described by at least an area size, aspect ratios, and wire connections. Action masks are generated for respective ones of the aspect ratios to block out a subset of unoccupied grid cells based on design rules that optimize macro placement. Then, by applying the action masks on the probability distribution, a masked probability distribution is generated. Based on the masked probability distribution, a location on the grid is selected for placing the macro cluster with a chosen aspect ratio.
Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.