Patents by Inventor Ming Yu

Ming Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor devices with a double sided word line structure and methods of manufacture
    Patent number: 11856876
    Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Cheng-Chun Chang
  • BOP ELASTOMER SEALS WITH IMPROVED SELF-HEALING
    Publication number: 20230407161
    Abstract: A self-healing elastomeric compound for use in blowout preventer packers includes one or more elastomers, carbon black, silica, and a self-healing agent evenly distributed throughout the compound.
    Type: Application
    Filed: June 15, 2023
    Publication date: December 21, 2023
    Applicant: Hydril USA Distribution LLC
    Inventors: Joseph Incavo, Nusrat Farzana, Ming Yu Huang
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
    Publication number: 20230411215
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.
    Type: Application
    Filed: July 28, 2023
    Publication date: December 21, 2023
    Inventors: Shao-Ming YU, Tung Ying LEE, Wei-Sheng YUN, Fu-Hsiang YANG
  • Semiconductor memory devices with electrically isolated stacked bit lines and methods of manufacture
    Patent number: 11849655
    Abstract: A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Shao-Ming Yu, Kai-Tai Chang
  • Light-transmitting decorated molding article and method of fabricating the same
    Patent number: 11840008
    Abstract: A method of fabricating a decorated molding article includes forming an all-in-one coating on a substrate and performing a curing step, thereby forming a composite layer structure with a protective effect, a color effect, and a bonding effect. The composite layer structure may form a molded film with better physical properties (e.g., higher hardness, better protection effect, and the like) after the blister molding process. Therefore, the molded film of the embodiments may be applied to a laser engraving process to form a variety of light-transmitting decorated molding articles.
    Type: Grant
    Filed: October 24, 2021
    Date of Patent: December 12, 2023
    Assignee: Jin Ya Dian Technology Co., Ltd.
    Inventors: Che-Ming Yu, Kuo-Liang Ying
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE
    Publication number: 20230389452
    Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Cheng-Chun Chang
  • PHASE CHANGE MEMORY DEVICE HAVING TAPERED PORTION OF THE BOTTOM MEMORY LAYER
    Publication number: 20230380305
    Abstract: A device includes a bottom electrode, a first memory layer, a second memory layer, and a top electrode. The bottom electrode is over a substrate. The first memory layer is over the bottom electrode. A sidewall of the first memory layer is curved. The second memory layer is over the bottom memory layer. The top electrode is over the top memory layer.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Ying LEE, Shao-Ming YU, Yu-Chao LIN
  • SEMICONDUCTOR MEMORY DEVICES WITH ELECTRICALLY ISOLATED STACKED BIT LINES AND METHODS OF MANUFACTURE
    Publication number: 20230380310
    Abstract: A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Inventors: Tung Ying Lee, Shao-Ming Yu, Kai-Tai Chang
  • LOW-TEMPERATURE HYDROGEN OXIDATION SYSTEM
    Publication number: 20230364552
    Abstract: The invention provides a low-temperature hydrogen oxidation system comprising at least one hydrogen oxidation device, at least one hydrogen reaction module is disposed in the hydrogen oxidation device, at least one hydrogen reaction channel is formed in the hydrogen reaction module and is provided with at least one catalyst, the hydrogen oxidation device is provided with at least one gas inlet channel and at least one gas outlet channel to communicate with the hydrogen reaction channel, at least one cooling channel is further formed in the hydrogen oxidation device; and at least one gas humidifying device disposed at a position of the gas inlet channel.
    Type: Application
    Filed: August 24, 2022
    Publication date: November 16, 2023
    Inventors: Ming-Yu Yen, HSU-LIN CHANG, FU-YANG SHIH
  • PACKAGING STRUCTURE WITH MAGNETOCALORIC MATERIAL
    Publication number: 20230368950
    Abstract: A packaging structure with a magnetocaloric material, comprising a substrate, a plurality of electrical connection structures, a die, and a sealing compound. A magnetocaloric material is added to the substrate. The die is electrically connected to the substrate through the electrical connection structures, and then encapsulated with the sealing compound. When the packaging structure is turned on, the magnetocaloric material in the substrate creates a magnetocaloric effect, which can not only take away the temperature of the packaging structure through magnetic refrigeration, but also increase the temperature difference between the packaging structure and the outside, thereby improving the efficiency of heat dissipation.
    Type: Application
    Filed: May 11, 2022
    Publication date: November 16, 2023
    Inventors: Wen Nan Huang, Ching Kuo Chen, Chih Ming Yu, Hsiang Chi Meng, I Ming Lo
  • Sidewall protection for PCRAM device
    Patent number: 11818967
    Abstract: A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer. The memory cell includes a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the phase change element. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chao Lin, Yuan-Tien Tu, Shao-Ming Yu, Tung-Ying Lee
  • Method and related apparatus for integrating electronic memory in an integrated chip
    Patent number: 11817488
    Abstract: In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung Ying Lee, Shao-Ming Yu, Tzu-Chung Wang
  • MEMORY STACKS AND METHODS OF FORMING THE SAME
    Publication number: 20230363298
    Abstract: Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.
    Type: Application
    Filed: July 20, 2023
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Yu-Chao Lin
  • Oligomer (2,6-dimethylphenylene ether) together with fabrication method and cured product thereof
    Patent number: 11807716
    Abstract: An oligomer (2,6-dimethylphenylene ether) is provided. Its structure is shown as follows: which comprises separately independent hydrogen; alkyl or phenyl; separately independent —NR—, —CO—, —SO—, —CS—, —SO2—, —CH2—, —O—, null, —C(CH3)2—, or and a hydrogen, The features of the cured products include a high glass-transition temperature, a low dielectric feature, preferred thermal stability, and good flame retardancy. The present invention effectively controls the number-average molecular weight of the product to obtain excellent organic solubility.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: November 7, 2023
    Assignee: CPC Corporation, Taiwan
    Inventors: Sheng-De Li, Ching-Hsuan Lin, Yi-Hsuan Hsieh, Wei-Yen Chen, Way-Chih Hsu, Jui-Fu Kao, Ming-Yu Huang, Jann-Chen Lin, Yih-Ping Wang
  • NETWORK RESOURCE REQUEST METHOD AND RELATED DEVICE THEREOF
    Publication number: 20230354105
    Abstract: The present disclosure relates to a network resource request method. An example method includes obtaining network intent information of a user, where the network intent information includes quantity information of a terminal device and service requirement information of the terminal device. The example method further includes performing classification representation on the network intent information based on an intent model, where the intent model includes a terminal device set, a service flow set, and a mapping relationship between the terminal device set and the service flow set. The example method further includes generating service level agreement (SLA) information based on a representation result of the intent model and sending the SLA information to an element management system.
    Type: Application
    Filed: June 21, 2023
    Publication date: November 2, 2023
    Inventors: Fengbao WANG, Shanshan WANG, Ming YU, Jun YANG
  • Phase change memory device having tapered portion of the bottom memory layer
    Patent number: 11805712
    Abstract: A phase change memory device includes a bottom conductive line, a dielectric layer, a bottom memory layer, and a top electrode. The dielectric layer covers the bottom conductive line. The bottom memory layer is in the dielectric layer and is electrically connected to the bottom conductive line. The bottom memory layer includes a tapered portion and a neck portion. The tapered portion is over the bottom conductive line and is tapered toward the bottom conductive line. The neck portion is directly between the tapered portion and the bottom conductive line. The neck portion has a substantially constant width. The top electrode is over and electrically connected to the bottom memory layer.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: October 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Yu-Chao Lin
  • Phosphinated (2,6-dimethylphenyl ether) oligomer, preparation method thereof and cured product
    Patent number: 11787904
    Abstract: A phosphinated (2,6-dimethylphenyl ether) oligomer, preparation method thereof and cured product. The phosphinated (2,6-dimethylphenyl ether) oligomer includes a structure represented by Formula (1): wherein X is a single bond, —CH2—, —O—, —C(CH3)2— or R?0, R0, R1, R2 and R3 are independently hydrogen, C1-C6 alkyl or phenyl; n and m are independently an integer from 0 to 300; p and q are independently an integer from 1 to 4; Y is hydrogen, U and V are independently an aliphatic structure.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: October 17, 2023
    Assignee: CPC CORPORATION, TAIWAN
    Inventors: Sheng-De Li, Ching-Hsuan Lin, Cheng-Liang Liu, Jun-Cheng Ye, You-Lin Shih, Yu An Lin, Wei-Yen Chen, Way-Chih Hsu, Jui-Fu Kao, Ming-Yu Huang, Jann-Chen Lin, Yih-Ping Wang
  • Memory stacks and methods of forming the same
    Patent number: 11793092
    Abstract: Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: October 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Yu-Chao Lin
  • MICROPHONE DEVICE AND AUDIO SIGNAL PROCESSING METHOD
    Publication number: 20230328431
    Abstract: A microphone device includes a first circuit board, a plurality of first microphones and a plurality of second microphones. The first microphones are disposed on the first circuit board and arranged along a first spiral about the reference point. The second microphones are disposed on the first circuit board and arranged along a second spiral about the reference point, wherein the second spiral is non-overlapped with the first spiral. The first microphones and the second microphones are point-symmetrical with respect to the reference point, the first microphones and the second microphones form a plurality of microphone sets, and each of the microphone sets comprises one of the first microphones and one of the second microphones which are point-symmetrical with respect to the reference point.
    Type: Application
    Filed: April 7, 2023
    Publication date: October 12, 2023
    Applicant: AVER INFORMATION INC.
    Inventor: Ming-Yu LIU
  • PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230317585
    Abstract: A package structure includes a first redistribution circuit structure, a semiconductor die, a connecting film, and a second redistribution circuit structure. The first redistribution circuit structure includes a dielectric structure and a routing structure disposed therein, where the dielectric structure includes a trench exposing the routing structure. The semiconductor die is disposed on and electrically coupled to the first redistribution circuit structure. The connecting film is disposed in the trench and between the semiconductor die and the first redistribution circuit structure, and the semiconductor die is thermally coupled to the routing structure through the connecting film.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Wei-Jhan Tsai, Sheng-Feng Weng, Ching-Yao Lin, Ming-Yu Yen, Kai-Fung Chang, Chih-Wei Lin, Ching-Hua Hsieh