Abstract: An encoding method includes: a first matching block of a current block is determined; motion compensation enhancement is performed on the first matching block to obtain at least one second matching block; motion information of the current block is determined according to the at least one second matching block; and the current block is encoded according to the motion information.

Abstract: The present disclosure relates to a system, a method and a computer-readable medium for rendering a streaming on a user terminal. The method includes rendering the streaming in a first mode, receiving an environment parameter of the user terminal, receiving a timing when the user terminal closes the streaming, determining a threshold value of the environment parameter based on the timing the user terminal closes the streaming, receiving an updated environment parameter of the user terminal, and rendering the streaming in a second mode if the updated environment parameter meets the threshold value. The second mode includes fewer data objects than the first mode or includes a downgraded version of a data object in the first mode for the rendering. The present disclosure can customize the rendering mode for each user and maximize the satisfaction of viewing streaming for each user.

Abstract: A point cloud positioning error detection method, performed by a processing device, includes: obtaining a plurality of pieces of first point data and a target point cloud map, wherein the target point cloud map includes a plurality of pieces of target point data, registering the first point data and the target point data to obtain a plurality of pieces of second point data, selecting a plurality of pieces of third point data from the second point data according to a first default distance, calculating a plurality of matching scores of the third point data relative to the target point data, obtaining a plurality of step vectors corresponding to the third point data, respectively, when said registering converges, and obtaining a plurality of effective values according to directions of the step vectors, and outputting a localization fault detection result based on an intersection of the matching scores and the effective values.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.

Abstract: Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a memory cell overlying a substrate. A lower via underlies the memory cell. The lower via is laterally offset from the memory cell by a lateral distance. A first conductive layer is disposed vertically between the memory cell and the lower via and comprising a first material. The first conductive layer continuously extends along the lateral distance. A second conductive layer extends across an upper surface of the first conductive layer and comprises a second material different from the first material. A bottom surface of the second conductive layer is aligned with a bottom surface of the memory cell.

Abstract: A well cementing method is described for improving cementing quality by controlling the hydration heat of cement slurry. By controlling the degree and/or rate of hydration heat release from cement slurry, the method improves the hydration heat release during formation of cement with curing of cement slurry, improves the binding quality between the cement and the interfaces, and in turn improves the cementing quality at the open hole section and/or the overlap section. The cementing method improves cementing quality of oil and gas wells and reduces the risk of annular pressure.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Abstract: An electronic device is provided, including a substrate and a plurality of electronic units disposed on the substrate. The substrate includes a first edge extending along a first direction and a second edge extending along a second direction. The electronic units include first, second, and third electronic units arranged adjacently along the first direction. The first electronic unit is closer to the second edge than the third electronic unit. A pitch between the second and third electronic units is greater than a pitch between the first and second electronic units. The electronic units include fourth, fifth and sixth electronic units arranged adjacently along the second direction. The fourth electronic unit is closer to the first edge than the sixth electronic unit. A pitch between the fourth and fifth electronic units is greater than a pitch between the fifth and sixth electronic units.

Abstract: The present disclosure generally relates to a dual free layer (DFL) read head and methods of forming thereof. In one embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a stripe height of the DFL sensor, depositing a rear bias (RB) adjacent to the DFL sensor, defining a track width of the DFL sensor and the RB, and depositing synthetic antiferromagnetic (SAF) soft bias (SB) side shields adjacent to the DFL sensor. In another embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a track width of the DFL sensor, depositing SAF SB side shields adjacent to the DFL sensor, defining a stripe height of the DFL sensor and the SAF SB side shield, depositing a RB adjacent to the DFL sensor and the SAF SB side shield, and defining a track width of the RB.

Abstract: An electrostatic sensing system configured to sense an electrostatic information of a fluid inside a fluid distribution component and including an electrostatic sensing assembly, a signal amplifier and an analog-to-digital converter. The electrostatic sensing assembly includes a sensing component, and a shield. The sensing component is configured to be disposed at the fluid distribution component. The sensing component is disposed through the fluid distribution component so as to be partially located in the fluid distribution component. The shield surrounds a part of the sensing component that is located in the fluid distribution component. At least part of the shield is located on an upstream side of the sensing component. The signal amplifier is electrically connected to the sensing component. The analog-to-digital converter is electrically connected to the signal amplifier. The shield has an opening spaced apart from the sensing component.

Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

Abstract: In some embodiments, the present disclosure relates to a memory device that includes a spin orbit torque (SOT) layer arranged over a substrate. A magnetic tunnel junction (MTJ) structure may be arranged over the SOT layer. The MTJ structure includes a free layer, a reference layer, and a diffusion barrier layer disposed between the free layer and the reference layer. A first conductive wire is arranged below the SOT layer and coupled to the SOT layer. A second conductive wire is arranged below the SOT layer and coupled to the SOT layer. A third conductive wire is arranged over the MTJ structure. The memory device further includes a first selector structure arranged between the first conductive wire and the SOT layer.

Abstract: A remanufacturing method of a drill includes providing a drill with a worn-out area. The drill comprises: a shank part; and a flute part arranged on one end of the shank part. A chisel edge is formed on the front end of the flute part, and the radius of any one of the cross section of the chisel edge is defined as a core thickness; a first blade and a second blade with tilt directions toward the shank part are formed on the two sides of the chisel edge. The first circumferential surface of the first blade and the second circumferential surface of the second blade are respectively extended and spiraled toward the shank part along a periphery of the flute part and form two helical cutting edges, a first debris-discharging groove and a second debris-discharging groove. The first blade comprises a first cutting edge. The first cutting edge and the first circumferential surface define the worn-out area.

Abstract: An IC package comprises a substrate; a semiconductor die with a top surface, wherein the semiconductor die is stacked over the substrate; a vapor chamber stacked over the semiconductor die, wherein the vapor chamber comprises a proximal portion and a distal portion, the proximal portion covers the top surface of the semiconductor die; and an encapsulating case encapsulating the substrate, the semiconductor die and the vapor chamber, wherein the proximal portion of the vapor chamber is within the encapsulating case, and the distal portion of the vapor chamber extends from a wall of the encapsulating case.

Abstract: A UE includes an application processor that generates application data to be transmitted to a base station. The UE also includes a modem that determines a downlink active time period. The modem or the application processor determines whether the application data is available before the downlink active time period. The modem or the application processor withholds the transmission of the application data to the base station until the downlink active time period. The modem transmits the application data to the base station during the downlink active time period.

Abstract: A User Equipment (UE) including a wireless transceiver and a controller is provided. The wireless transceiver performs wireless transmission and reception to and from one or more peer UEs. The controller determines a Sidelink (SL) Discontinuous Reception (DRX) configuration set, and applies the SL DRX configuration set to enable a DRX operation for SL communications with the peer UEs via the wireless transceiver; wherein the SL DRX configuration set is determined based on one of the following: one or more types of one or more SL services which the UE is participating with the peer UEs; one or more SL DRX configurations received from the peer UEs; and control information received from a Base Station (BS).