Abstract: A User Equipment (UE) including a wireless transceiver and a controller is provided. The wireless transceiver performs wireless transmission and reception to and from one or more peer UEs. The controller determines a Sidelink (SL) Discontinuous Reception (DRX) configuration set, and applies the SL DRX configuration set to enable a DRX operation for SL communications with the peer UEs via the wireless transceiver; wherein the SL DRX configuration set is determined based on one of the following: one or more types of one or more SL services which the UE is participating with the peer UEs; one or more SL DRX configurations received from the peer UEs; and control information received from a Base Station (BS).

Abstract: A method of UE prioritizing and multiplexing simultaneous sidelink relay data for Logical Channel Prioritization (LCP) procedure in new radio (NR) system is proposed. UE can provide traffic prioritization based on traffic category when UE has simultaneous traffic from more than one traffic categories to transmit. The sidelink relay traffic prioritization is then used for transmission interface and resource selection, and data multiplexing prioritization on the basis of sidelink relay architecture. Specifically, a method on how to perform the corresponding logical channel prioritization (LCP) operation for MAC PDU multiplexing is provided. LCP restriction is considered to determine which classes of traffic can be multiplexed into the same MAC PDU together. Priority of multiplexing is also applied to determine the order and the amount of traffic to be included in the MAC PDU.

Abstract: An electrochromic mirror module including a cover lens, a connecting layer, and an electrochromic device is provided. The connecting layer includes a first absorbing material. The connecting layer connects between the cover lens and the electrochromic device. The electrochromic mirror module is configured to receive an incident light, and the incident light sequentially transmits through the cover plate and the connection layer to reach the electrochromic device. The first absorbing material is configured to absorb light of the incident light, whose wavelength falls in a first spectrum, and the wavelength of the first spectrum fall within the range of 570 nm to 720 nm.

Abstract: In some embodiments, the present disclosure relates to a memory device that includes a spin orbit torque (SOT) layer arranged over a substrate. A magnetic tunnel junction (MTJ) structure may be arranged over the SOT layer. The MTJ structure includes a free layer, a reference layer, and a diffusion barrier layer disposed between the free layer and the reference layer. A first conductive wire is arranged below the SOT layer and coupled to the SOT layer. A second conductive wire is arranged below the SOT layer and coupled to the SOT layer. A third conductive wire is arranged over the MTJ structure. The memory device further includes a first selector structure arranged between the first conductive wire and the SOT layer.

Abstract: Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.

Abstract: An electronic system is provided, which includes a host device and a display device. The host device includes a first signal conversion circuit and a first signal transmission circuit. The first signal conversion circuit is utilized for converting signals associated with the host device into a first universal serial bus signal. The display device includes a display panel, a second signal conversion circuit and a second signal transmission circuit. The second signal transmission circuit is utilized for receiving the first universal serial bus signal. The second signal conversion circuit is coupled to the second signal transmission circuit for converting the first universal serial bus signal into the signals associated with the host device. The first universal serial bus signal conforms to universal serial bus 4.

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Abstract: A memory device is provided. The memory device includes a substrate, a spin-orbit torque layer and a magnetic tunneling junction (MTJ). The MTJ stacks with the spin-orbit torque layer over the substrate and includes a synthetic free layer, a barrier layer and a reference layer. The synthetic free layer includes a synthetic antiferromagnetic structure, a first spacer layer and a free layer, wherein the synthetic antiferromagnetic structure is disposed between the spin-orbit torque layer and the free layer. The barrier layer is disposed beside the synthetic free layer. The reference layer is disposed beside the barrier layer.

Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.

Abstract: A method of radio link monitoring (RLM) can include performing a physical sidelink shared channel (PSSCH) transmission over a radio link between a Tx UE and a Rx UE in sidelink communications, receiving a HARQ feedback status corresponding to the PSSCH transmission from a physical layer, incrementing a count of a number of consecutive HARQ failure indications (e.g., represented by HARQ DTX) received for PSSCH transmissions over the radio link between the Tx UE and the Rx UE by 1 when the received HARQ feedback status is a HARQ failure indication, declaring a radio link failure (RLF) for the radio link between the Tx UE and the Rx UE when the count of the number of consecutive HARQ failure indications reaches a threshold, and resetting the count of the number of consecutive HARQ failure indications to 0 when the received HARQ feedback status is not a HARQ failure indication.

Abstract: An engineered vaccinia virus, a pharmaceutical composition containing the same, and methods for use in treating a subject in need using the same are provided. The engineered vaccinia virus includes a mutated viral sequence and a heterologous sequence. The mutated viral sequence is used for selective replication in tumor cells and/or activation of immune cells. The heterologous sequence encodes an immune co-stimulatory pathway activating molecule, immunomodulator gene, a truncated viral envelope gene, and/or a tumor suppressor. The heterologous sequence is stably incorporated into the genome of the engineered vaccinia virus. The pharmaceutical composition includes an effective amount of the engineered vaccinia virus and a pharmaceutical acceptable vehicle. The methods for use in treating the subject in need include administering the engineered vaccinia virus to the subject.

Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.

Abstract: A memory device and a memory circuit is provided. The memory device includes a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ), a read word line, a selector and a write word line. The MTJ stands on the SOT layer. The read word line is electrically connected to the MTJ. The write word line is connected to the SOT layer through the selector. The write word line is electrically connected to the SOT layer when the selector is turned on, and the write word line is electrically isolated from the SOT layer when the selector is in an off state.

Abstract: A rotatable cushioning pick-and-place device primarily comprises a motor, a body, a cushioning module and a pick-and-place module. The cushioning module is disposed in a first chamber of the body and comprises a rotary bearing which is connected to a drive shaft of the motor, and coupled to a driven shaft sleeve through a rotary follower. The rotary follower is driven by the rotary bearing to drive the driven shaft sleeve to rotate, thereby allowing the rotary bearing to displace relative to the driven shaft sleeve axially. The cushioning spring is arranged between the rotary bearing and the driven shaft sleeve. A first sealing ring and a second sealing ring of the pick-and-place module are fixed on the body to cooperatively and air-tightly seal the second chamber.

Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.

Abstract: A non-volatile memory device includes a substrate, a stacked structure, an anti-fuse gate, a gate dielectric layer, a first doping region, and a second doping region. The stacked structure is formed on the substrate and includes a floating gate, a select logic gate, a logic gate dielectric layer, and an inter-polysilicon layer dielectric layer. The select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the inter-polysilicon layer dielectric layer is disposed between the floating gate and the select logic gate. The anti-fuse gate is disposed on the substrate, and the gate dielectric layer is disposed between the anti-fuse gate and the substrate. The first doping region is formed in the substrate at one side of the floating gate. The second doping region is formed in the substrate between the floating gate and the anti-fuse gate.

Abstract: An automatic battery replacement apparatus, a moving platform, and a rechargeable battery are provided. The moving platform includes a movable carrier and the rechargeable battery assembled in the movable carrier. The movable carrier includes a carrying body and a moving component that is assembled to the carrying body. The carrying body has a power supply slot recessed in an outer surface thereof, and an inner lateral wall of the power supply slot is in a shape of an arc having a central angle that is less than or equal to 180 degrees. The moving component is configured to move on a working surface. The rechargeable battery has a matching structure configured to be engaged with a driving gear. The rechargeable battery is configured to be rotated along the inner lateral wall of the power supply slot by having the matching structure engaged with the driving gear.

Abstract: An automatic nut screwing device includes a positioning mold plate, a screw shaft, driving gear elements having driving gears, and transmission screwing elements having transmission screw gear units, bolt heads and bolt bodies. The transmission screw gear unit engages an upper out surface of the bolt head. The bolt head of each transmission screw element is fixed with the positioning mold plate. The shaft engaging portion engages with the transmission screw gear unit. The transmission screw gear unit engages with the driving gears such that the transmission screw gear unit is driven to rotate by the shaft engaging portion. A nut socket placing element has nut sockets when the screw shaft is axially rotated to enable the shaft engaging portion of the screw shaft to drive the transmission screw elements, thereby successively rotating elements that result in screw body being rotated to screw with the nut.

Abstract: A memory device and a memory circuit is provided. The memory device includes a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ), a read word line, a selector and a write word line. The MTJ stands on the SOT layer. The read word line is electrically connected to the MTJ. The write word line is connected to the SOT layer through the selector. The write word line is electrically connected to the SOT layer when the selector is turned on, and the write word line is electrically isolated from the SOT layer when the selector is in an off state.

Abstract: A memory device and a memory circuit is provided. The memory device includes a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ), a read word line, a selector and a write word line. The MTJ stands on the SOT layer. The read word line is electrically connected to the MTJ. The write word line is connected to the SOT layer through the selector. The write word line is electrically connected to the SOT layer when the selector is turned on, and the write word line is electrically isolated from the SOT layer when the selector is in an off state.