Patents by Inventor Min-Suk Lee

Min-Suk Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230414108
    Abstract: In a temperature sensor, a wearable device comprising the temperature sensor, and a core temperature measurement method using the temperature sensor, the temperature sensor includes a sensing unit and a substrate. The sensing unit includes a base part, a measuring part mounted on the base part and configured to measure a temperature of a subject body by making contact with the subject body, and a cover part configured to cover the measuring part. The sensing unit is mounted on the substrate. A plurality of slits is formed around a first area of the substrate, and the sensing unit is mounted at the first area of the substrate.
    Type: Application
    Filed: September 23, 2021
    Publication date: December 28, 2023
    Applicant: OSONG MEDICAL INNOVATION FOUNDATION
    Inventors: Seung Rag LEE, Sung Jun HONG, Byung Jun PARK, Byung Yeun KIM, Min Suk LEE
  • Patent number: 10874156
    Abstract: The present invention relates to a heat-storing and retaining fleece using a polyester yarn containing composite metal oxide particles. The heat-storing and retaining fleece of the present invention exhibits an excellent far-infrared emission property, an excellent heat-storing and retaining property, excellent spinning processability, and excellent dyeability.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: December 29, 2020
    Assignee: HYOSUNG TNC CORPORATION
    Inventors: Sung Jin Oh, Min Suk Lee
  • Patent number: 10777742
    Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
  • Publication number: 20200098984
    Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 26, 2020
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
  • Patent number: 10490741
    Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: November 26, 2019
    Assignee: SK hynix Inc.
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
  • Patent number: 10329694
    Abstract: The present invention relates to a method for producing a functional yarn, in which zirconium phosphate having a multiple-layered structure is used as a deodorizing material and a melted polymer is spun through a spinning nozzle having a multi-lobal sectional shape. According to the present invention, the melted polymer contains layered fine zirconium phosphate inorganic particles having low hardness, and thus the abrasion of production process equipment can be minimized during fiber production and also an excellent deodorizing property and an excellent sweat-absorbing and quick-drying property are exhibited.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: June 25, 2019
    Assignee: HYOSUNG TNC CORPORATION
    Inventors: Tae Gyun Lee, Min Suk Lee, Jun Young Park
  • Patent number: 10305030
    Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
  • Patent number: 10240258
    Abstract: The present invention is directed to a method for preparing a polyester fiber, the method including: mixing 5-50 wt % of composite metal oxide particles, including a tungsten-based oxide, a cesium-based oxide, an antimony-based oxide, an indium-based oxide, and a tin-based oxide, with 40-90 wt % of one or two types of organic solvents selected from among alcohol, ketone, and acetates, 0.4-20 wt % of polyvinyl butyral, i.e., polymer, and 2-30 wt % of calcium stearate or magnesium stearate to obtain a mixture, and stirring and grinding the mixture to prepare a dispersion liquid; drying the dispersion liquid to prepare a powdered additive; mixing 1-30 wt % of the additive with polyester chips to obtain a mixture and melting this mixture to prepare master batch chips; and mixing 1-10 wt % of the master batch chips with general polyester chips to obtain a mixture, and melting and spinning this mixture.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: March 26, 2019
    Assignee: HYOSUNG TNC CORPORATION
    Inventors: Sung Jin Oh, Min Suk Lee
  • Patent number: 10205089
    Abstract: This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes an interlayer dielectric layer formed over a substrate and having a contact hole; a lower contact filled in a part of the contact hole; and a variable resistance element which is disposed over and coupled to the lower contact, and has a first part filled in the contact hole and a second part disposed over the first part and protruding over the interlayer dielectric layer, wherein the first part includes a first metal which has a higher electron affinity than a component included in the second part, and an oxide of the first metal is an insulating material.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: February 12, 2019
    Assignee: SK hynix Inc.
    Inventors: Jae-Hong Kim, Min-Suk Lee
  • Patent number: 10186307
    Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a contact plug; a first stack structure disposed over the contact plug and coupled to the contact plug, wherein the first stack structure includes a pinning layer controlling a magnetization of a pinned layer; and a second stack structure disposed over the first stack structure and coupled to the first stack structure, wherein the second stack structure includes a MTJ (Magnetic Tunnel Junction) structure which includes the pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein a width of the first stack structure is larger than a width of the contact plug and a width of the second stack structure.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: January 22, 2019
    Assignee: SK hynix Inc.
    Inventor: Min-Suk Lee
  • Patent number: 10043562
    Abstract: In one implementation, an electronic device is provided to include a semiconductor memory, wherein the semiconductor memory may include: a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a changeable magnetization direction free layer, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer, and the electronic device may further include, in a first direction in which the free layer, the tunnel barrier layer and the pinned layer are arranged, a first permanent magnet having a first surface facing a first surface of the variable resistance element and spaced from the variable resistance element, wherein a magnetic field generated by the first permanent magnet may have a direction which offsets or reduces an influence of a stray field generated by the pinned layer.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 7, 2018
    Assignee: SK hynix Inc.
    Inventors: June-Seo Kim, Min-Suk Lee, Jung-Hwan Moon, Bo-Kyung Jung, Jeong-Myeong Kim, Ji-Hun Park
  • Publication number: 20180130945
    Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 10, 2018
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
  • Publication number: 20180102154
    Abstract: In one implementation, an electronic device is provided to include a semiconductor memory, wherein the semiconductor memory may include: a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a changeable magnetization direction free layer, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer, and the electronic device may further include, in a first direction in which the free layer, the tunnel barrier layer and the pinned layer are arranged, a first permanent magnet having a first surface facing a first surface of the variable resistance element and spaced from the variable resistance element, wherein a magnetic field generated by the first permanent magnet may have a direction which offsets or reduces an influence of a stray field generated by the pinned layer.
    Type: Application
    Filed: April 21, 2017
    Publication date: April 12, 2018
    Inventors: June-Seo Kim, Min-Suk Lee, Jung-Hwan Moon, Bo-Kyung Jung, Jeong-Myeong Kim, Ji-Hun Park
  • Patent number: 9938642
    Abstract: The present invention relates to a method for producing a multifunctional polyester fiber, including: mixing a polyester master batch chip, containing cesium tungsten oxide-based particles, with a general polyester chip; spinning the mixture to form a spun fiber; and cooling the spun fiber using a cooling device having a rotational outflow quenching unit and a nozzle-warming heater, and to a fiber produced by the method. The multifunctional polyester fiber according to the present invention exhibits excellent far-infrared emission properties, thermal storage/insulation properties, spinning processability, and dyeability.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: April 10, 2018
    Assignees: Hyosung Corporation, Nano-Vision Tech Co., Ltd.
    Inventors: Sung Jin Oh, Min Suk Lee, Young Un Oh
  • Publication number: 20180082727
    Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a contact plug; a first stack structure disposed over the contact plug and coupled to the contact plug, wherein the first stack structure includes a pinning layer controlling a magnetization of a pinned layer; and a second stack structure disposed over the first stack structure and coupled to the first stack structure, wherein the second stack structure includes a MTJ (Magnetic Tunnel Junction) structure which includes the pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein a width of the first stack structure is larger than a width of the contact plug and a width of the second stack structure.
    Type: Application
    Filed: November 27, 2017
    Publication date: March 22, 2018
    Inventor: Min-Suk Lee
  • Patent number: 9900577
    Abstract: An apparatus and a method for synchronizing left and right streams in a stationary/mobile hybrid 3DTV are disclosed. The apparatus according to an exemplary embodiment may synchronize content streams corresponding to left and right images using a timestamp pairing mode, a timestamp offset mode, and a network time protocol (NTP) synchronization mode.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: February 20, 2018
    Assignees: Electronics and Telecommunications Research Institute, KAI MEDIA CO., Hidea Solutions Co., Ltd., KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATION
    Inventors: Sung Hoon Kim, Joo Young Lee, Jin Soo Choi, Jin Woong Kim, Suk Jin Hong, Jin Suk Kwak, Min Suk Lee, Dong Wook Kang, Kyeong Hoon Jung
  • Patent number: 9894341
    Abstract: Provided is a video providing method and a video playing method for a three-dimensional (3D) video, and an apparatus for performing the methods. The video providing method may transmit a reconstruction mode for reconstructing a low-resolution additional video having lower resolution than a high-resolution reference video.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: February 13, 2018
    Assignees: Electronics and Telecommunications Research Institute, KAI MEDIA CO., Hidea Solutions Co., Ltd., Kookmin University Industry Academy Cooperation Foundation
    Inventors: Sung Hoon Kim, Joo Young Lee, Hyon Gon Choo, Jin Soo Choi, Jin Woong Kim, Suk Jin Hong, Jin Suk Kwak, Min Suk Lee, Dong Wook Kang, Kyeong Hoon Jung
  • Patent number: 9893121
    Abstract: According to one embodiment, a magnetic memory includes a first metal layer including a first metal, a second metal layer on the first metal layer, the second metal layer including a second metal which is more easily oxidized than the first metal, the second metal layer having a first sidewall portion which contacts the first metal layer, and the second metal layer having a second sidewall portion above the first sidewall portion, the second sidewall portion which steps back from the first sidewall portion, a magnetoresistive element on the second metal layer, a third metal layer on the magnetoresistive element, and a first material which contacts a sidewall portion of the magnetoresistive element and the second sidewall portion of the second metal layer, the first material including an oxide of the second metal.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: February 13, 2018
    Assignees: Toshiba Memory Corporation, SK Hynix, Inc.
    Inventors: Yasuyuki Sonoda, Masahiko Nakayama, Min Suk Lee, Masatoshi Yoshikawa, Kuniaki Sugiura, Ji Hwan Hwang
  • Patent number: 9865806
    Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: January 9, 2018
    Assignee: SK hynix Inc.
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
  • Patent number: 9847375
    Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; a plurality of variable resistance elements formed over the substrate and arranged as a matrix, spacer patterns formed over the substrate to surround the variable resistance elements in the matrix with a thickness sufficient to define contact holes between the variable resistance elements, and a source line contact buried in the contact hole.
    Type: Grant
    Filed: September 5, 2015
    Date of Patent: December 19, 2017
    Assignee: SK hynix Inc.
    Inventor: Min-Suk Lee