Patents by Inventor Mirmajid Seyyedy

Mirmajid Seyyedy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stacked 1T-nmemory cell structure
    Patent number: 7042749
    Abstract: This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: May 9, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Hasan Nejad, Mirmajid Seyyedy
  • Method and apparatus for testing a memory device with compressed data using a single output
    Publication number: 20060090108
    Abstract: A method and apparatus for testing a memory device with compressed data using multiple clock edges is disclosed. In one embodiment of the present invention data is written to cells in a memory device, the cells are read to generate read data, the read data is compressed to generate test data, and the test data is produced at a single output on edges of a clock signal.
    Type: Application
    Filed: December 8, 2005
    Publication date: April 27, 2006
    Inventors: Mirmajid Seyyedy, Mark Thomann
  • Stacked columnar 1T-MTJ structure and its method of formation and operation
    Patent number: 7023743
    Abstract: This invention relates to an array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of cells each column being provided in a respective stacked memory layer.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: April 4, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Hasan Nejad, Mirmajid Seyyedy
  • Method and apparatus for testing a memory device with compressed data using a single output
    Patent number: 6976195
    Abstract: A method and apparatus for testing a memory device with compressed data using multiple clock edges is disclosed. In one embodiment of the present invention data is written to cells in a memory device, the cells are read to generate read data, the read data is compressed to generate test data, and the test data is produced at a single output on edges of a clock signal.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: December 13, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Mirmajid Seyyedy, Mark R. Thomann
  • Stacked columnar 1T-nMTj MRAM structure and its method of formation and operation
    Publication number: 20050226038
    Abstract: This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.
    Type: Application
    Filed: June 2, 2005
    Publication date: October 13, 2005
    Inventors: Hasan Nejad, Mirmajid Seyyedy
  • Stacked 1T-nmemory cell structure
    Publication number: 20050226041
    Abstract: This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.
    Type: Application
    Filed: June 13, 2005
    Publication date: October 13, 2005
    Inventors: Hasan Nejad, Mirmajid Seyyedy
  • Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation
    Publication number: 20050226037
    Abstract: This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.
    Type: Application
    Filed: June 2, 2005
    Publication date: October 13, 2005
    Inventors: Hasan Nejad, Mirmajid Seyyedy
  • Stacked 1T-nMTJ MRAM structure
    Patent number: 6940748
    Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another a plurality of MRAM array layers arranged in a “Z” axis direction.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: September 6, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Hasan Nejad, Mirmajid Seyyedy
  • Magnetic tunneling junction antifuse device
    Publication number: 20050190620
    Abstract: An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the fixed magnetic layer and the soft magnetic layer. The MRAM cells are all formed simultaneously and at least some of the MRAM cells are designed to function as antifuse devices whereby the application of a selected electrical potential can short the antifuse device to thereby affect the functionality of the MRAM device.
    Type: Application
    Filed: May 6, 2005
    Publication date: September 1, 2005
    Inventors: Mirmajid Seyyedy, Mark Tuttle, Glen Hush
  • Columnar 1T-nMemory cell structure and its method of formation and operation
    Publication number: 20050162883
    Abstract: A memory array architecture incorporates certain advantages from both cross-point and 1T-1Cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of memory cells, each column being provided in a respective stacked memory layer.
    Type: Application
    Filed: August 25, 2004
    Publication date: July 28, 2005
    Inventors: Hasan Nejad, Mirmajid Seyyedy
  • Stacked IT-nMTJ MRAM structure
    Publication number: 20050162898
    Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.
    Type: Application
    Filed: March 17, 2005
    Publication date: July 28, 2005
    Inventors: Hasan Nejad, Mirmajid Seyyedy
  • Magnetic tunneling junction antifuse device
    Patent number: 6919613
    Abstract: An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the fixed magnetic layer and the soft magnetic layer. The MRAM cells are all formed simultaneously and at least some of the MRAM cells are designed to function as antifuse devices whereby the application of a selected electrical potential can short the antifuse device to thereby affect the functionality of the MRAM device.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: July 19, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Mirmajid Seyyedy, Mark E. Tuttle, Glen E. Hush
  • Stacked 1T-nMTJ MRAM structure
    Patent number: 6882566
    Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: April 19, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Hasan Nejad, Mirmajid Seyyedy
  • Stacked columnar resistive memory structure and its method of formation and operation
    Patent number: 6882553
    Abstract: This invention relates to a resistive memory array architecture which incorporates certain advantages from both cross-point and one transistor per cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the one transistor per cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of resistive memory cells each column being provided in a respective stacked memory layer.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: April 19, 2005
    Assignee: Micron Technology Inc.
    Inventors: Hasan Nejad, Mirmajid Seyyedy
  • Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation
    Patent number: 6879516
    Abstract: This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: April 12, 2005
    Assignee: Micron Technology Inc.
    Inventors: Hasan Nejad, Mirmajid Seyyedy
  • Stacked 1T-nMTJ MRAM structure
    Publication number: 20040264242
    Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.
    Type: Application
    Filed: July 22, 2004
    Publication date: December 30, 2004
    Inventors: Hasan Nejad, Mirmajid Seyyedy
  • Flip chip technique for chip assembly
    Patent number: 6831361
    Abstract: An apparatus for connecting one substrate, such as a flip-chip type semiconductor die, to an opposing substrate, such as a silicon wafer, printed circuit board, or other substrate is disclosed. Each substrate has a plurality of conductive bumps on its facing surface wherein the conductive bumps on each substrate are the mirror-image of the other substrate. The substrates are attached to one another in a manner in which the conductive bumps on one substrate form an electrical contact with its respective conductive bumps on the opposing substrate without mechanical attachment.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: December 14, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Mirmajid Seyyedy
  • Hybrid MRAM array structure and operation
    Publication number: 20040213044
    Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.
    Type: Application
    Filed: May 18, 2004
    Publication date: October 28, 2004
    Inventors: Mirmajid Seyyedy, Glen Hush
  • Magnetic tunneling junction antifuse device
    Publication number: 20040188799
    Abstract: An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the fixed magnetic layer and the soft magnetic layer. The MRAM cells are all formed simultaneously and at least some of the MRAM cells are designed to function as antifuse devices whereby the application of a selected electrical potential can short the antifuse device to thereby affect the functionality of the MRAM device.
    Type: Application
    Filed: April 8, 2004
    Publication date: September 30, 2004
    Inventors: Mirmajid Seyyedy, Mark E. Tuttle, Glen E. Hush
  • Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation
    Publication number: 20040165421
    Abstract: This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.
    Type: Application
    Filed: February 24, 2004
    Publication date: August 26, 2004
    Inventors: Hasan Nejad, Mirmajid Seyyedy