Abstract: This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

Abstract: An apparatus and a method for connecting one substrate, such as a flip-chip type semiconductor die, to an opposing substrate, such as a silicon wafer, printed circuit board, or other substrate. Each substrate has a plurality of conductive bumps on its facing surface wherein the conductive bumps on each substrate are the mirror-image of the other substrate. The substrates are attached to one another in a manner in which the conductive bumps on one substrate form an electrical contact with its respective conductive bumps on the opposing substrate without mechanical attachment.

Abstract: The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for memory devices in relatively few steps. Embodiments of the invention further include memory devices with metallization layers having unequal pitch dimensions in different areas of the chip, thereby permitting simultaneous fabrication of array electrodes and electrical interconnects in different areas of the chip. This reduces the number of fabrication steps used to make interconnects, thereby speeding up fabrication and reducing production costs.

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract: A method and apparatus for selecting a rowline in a MRAM device. A rowline select circuit is provided on a first side of each rowline and connects the rowline to ground when a memory cell in the rowline is being written to and to a voltage source when a memory cell in the rowline is being read. A rowline stack select circuit is provided on the second side of each rowline and is connected to one rowline on each plane of memory. When a memory cell is being accessed, the rowline containing that memory cell as well as each other rowline connected to the same rowline stack select circuit are connected to a current source.

Abstract: An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the fixed magnetic layer and the soft magnetic layer. The MRAM cells are all formed simultaneously and at least some of the MRAM cells are designed to function as antifuse devices whereby the application of a selected electrical potential can short the antifuse device to thereby affect the functionality of the MRAM device.

Abstract: A memory module, such as a SIMM or DIMM, is provided which incorporates error correction circuitry. The error correction circuitry identifies and corrects errors in communications between the memory module and an external processor. A reliable data processing system is also provided, incorporating the memory module comprising the error correction circuitry with a processor. The yield of manufactured chips is increased by presorting the memory chips which make up the memory module, such that a chip with one or more defective cells may be included in a memory module so long as no other chip has defective cells at the same location.

Abstract: This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract: This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1M architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transis is used to read multiple MRAM cells, which can be stacked vertically above one anot a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract: A method and apparatus for selecting a rowline in a MRAM device. A rowline select circuit is provided on a first side of each rowline and connects the rowline to ground when a memory cell in the rowline is being written to and to a voltage source when a memory cell in the rowline is being read. A rowline stack select circuit is provided on the second side of each rowline and is connected to one rowline on each plane of memory. When a memory cell is being accessed, the rowline containing that memory cell as well as each other rowline connected to the same rowline stack select circuit are connected to a current source.

Abstract: An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the fixed magnetic layer and the soft magnetic layer. The MRAM cells are all formed simultaneously and at least some of the MRAM cells are designed to function as antifuse devices whereby the application of a selected electrical potential can short the antifuse device to thereby affect the functionality of the MRAM device.

Abstract: A method and apparatus for selecting a rowline in a MRAM device. A rowline select circuit is provided on a first side of each rowline and connects the rowline to ground when a memory cell in the rowline is being written to and to a voltage source when a memory cell in the rowline is being read. A rowline stack select circuit is provided on the second side of each rowline and is connected to one rowline on each plane of memory. When a memory cell is being accessed, the rowline containing that memory cell as well as each other rowline connected to the same rowline stack select circuit are connected to a current source.

Abstract: A method and apparatus for selecting a rowline in a MRAM device. A rowline select circuit is provided on a first side of each rowline and connects the rowline to ground when a memory cell in the rowline is being written to and to a voltage source when a memory cell in the rowline is being read. A rowline stack select circuit is provided on the second side of each rowline and is connected to one rowline on each plane of memory. When a memory cell is being accessed, the rowline containing that memory cell as well as each other rowline connected to the same rowline stack select circuit are connected to a current source.

Abstract: A detector circuit for detecting a digital word matching a bit pattern programmed by fusible devices. The detector circuit includes decoder circuits coupled to first and second sense nodes, and a reference node, and further includes an evaluation circuit also coupled to the first and second sense nodes. The evaluation circuit senses the voltage of both sense nodes and produces a match signal according to these voltages. The voltage of the first and second sense nodes are determined by the programmed status of the decoder circuit and whether a matching bit is detected. The decoder circuit includes a fusible device, such as an antifuse, and a switch having a control terminal coupled to receive one bit of the digital word. An enable circuit may also be coupled to the detector circuit to either enable or disable operation of the detector circuit based on whether the enable circuit has been programmed.

Abstract: A memory module, such as a SIMM or DIMM, is provided which incorporates error correction circuitry. The error correction circuitry identifies and corrects errors in communications between the memory module and an external processor. A reliable data processing system is also provided, incorporating the memory module comprising the error correction circuitry with a processor. The yield of manufactured chips is increased by presorting the memory chips which make up the memory module, such that a chip with one or more defective cells may be included in a memory module so long as no other chip has defective cells at the same location.

Abstract: An apparatus for connecting one substrate, such as flip-chip type semiconductor die, to an opposing substrate, such as a silicon wafer, printed circuit board, or other substrate. Each substrate has a plurality of conductive bumps on its facing surface wherein the conductive bumps on each substrate are the mirror-image of the other substrate. The substrates are attached to one another in a manner in which the conductive bumps on one substrate form an electrical contact with its respective conductive bumps on the opposing substrate without mechanical attachment.

Abstract: A synchronous memory device is described which uses unique column select circuitry. The memory device pipelines address decode and column select operation to increase clock frequency. The column select circuitry includes latches and coupling circuits. The latches are used to latch a column select circuit. The coupling circuit isolates a column select signal from the memory cell columns until an enable signal is provided. The address decode can be combined with an enable signal to reduce the total number of latch circuits needed for a bank of memory cells.

Abstract: A dynamic memory has one digit line in place of two digit lines for sensing charges stored on memory cell capacitors. The memory device uses a low digit line pre-charge voltage to allow for a low supply voltage memory. In particular, one memory device embodiment uses sense amplifier nodes to provide a pre-charge supply to the digit line that is approximately a transistor threshold voltage above ground potential. By using the low pre-charge voltage, the memory device does not require boosted word line and isolation control voltages.