Patents by Inventor Mitsuhiro Ichijo

Mitsuhiro Ichijo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150179810
    Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. The semiconductor device includes an oxide semiconductor film over an insulating surface, an antioxidant film over the insulating surface and the oxide semiconductor film, a pair of electrodes in contact with the antioxidant film, a gate insulating film over the pair of electrodes, and a gate electrode which is over the gate insulating film and overlaps with the oxide semiconductor film. In the antioxidant film, a width of a region overlapping with the pair of electrodes is longer than a width of a region not overlapping with the pair of electrodes.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 25, 2015
    Inventors: Shunpei Yamazaki, Akihisa Shimomura, Yasumasa Yamane, Yuhei Sato, Tetsuhiro Tanaka, Masashi Tsubuku, Toshihiko Takeuchi, Ryo Tokumaru, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Toshiya Endo
  • Publication number: 20150140732
    Abstract: It is an object to drive a semiconductor device at high speed or to improve the reliability of the semiconductor device. In a method for manufacturing the semiconductor device, in which a gate electrode is formed over a substrate with an insulating property, a gate insulating film is formed over the gate electrode, and an oxide semiconductor film is formed over the gate insulating film, the gate insulating film is formed by deposition treatment using high-density plasma. Accordingly, dangling bonds in the gate insulating film are reduced and the quality of the interface between the gate insulating film and the oxide semiconductor is improved.
    Type: Application
    Filed: December 22, 2014
    Publication date: May 21, 2015
    Inventors: Mitsuhiro ICHIJO, Tetsuhiro TANAKA, Seiji YASUMOTO, Shun MASHIRO, Yoshiaki OIKAWA, Kenichi OKAZAKI
  • Publication number: 20150053975
    Abstract: In a transistor having a top-gate structure in which a gate electrode layer overlaps with an oxide semiconductor layer which faints a channel region with a gate insulating layer interposed therebetween, when a large amount of hydrogen is contained in the insulating layer, hydrogen is diffused into the oxide semiconductor layer because the insulating layer is in contact with the oxide semiconductor layer; thus, electric characteristics of the transistor are degraded. An object is to provide a semiconductor device having favorable electric characteristics. An insulating layer in which the concentration of hydrogen is less than 6×1020 atoms/cm3 is used for the insulating layer being in contact with oxide semiconductor layer which forms the channel region. Using the insulating layer, diffusion of hydrogen can be prevented and a semiconductor device having favorable electric characteristics can be provided.
    Type: Application
    Filed: September 30, 2014
    Publication date: February 26, 2015
    Inventors: Yuta ENDO, Toshinari SASAKI, Kosei NODA, Mizuho SATO, Mitsuhiro ICHIJO, Toshiya ENDO
  • Patent number: 8956934
    Abstract: An object is to provide a thin film transistor with small off current, large on current, and high field-effect mobility. A silicon nitride layer and a silicon oxide layer which is formed by oxidizing the silicon nitride layer are stacked as a gate insulating layer, and crystals grow from an interface of the silicon oxide layer of the gate insulating layer to form a microcrystalline semiconductor layer; thus, an inverted staggered thin film transistor is manufactured. Since crystals grow from the gate insulating layer, the thin film transistor can have a high crystallinity, large on current, and high field-effect mobility. In addition, a buffer layer is provided to reduce off current.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Miyako Nakajima, Hidekazu Miyairi, Toshiyuki Isa, Erika Kato, Mitsuhiro Ichijo, Kazutaka Kuriki, Tomokazu Yokoi
  • Patent number: 8951902
    Abstract: The present invention is provided in order to remove contamination due to contaminant impurities of the interfaces of each film which forms a TFT, which is the major factor that reduces the reliability of TFTs. By connecting a washing chamber and a film formation chamber, film formation can be carried out without exposing TFTs to the air during the time from washing step to the film formation step and it becomes possible to maintain the cleanliness of the interfaces of each film which form the TFT.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Shunpei Yamazaki
  • Patent number: 8927351
    Abstract: It is an object to drive a semiconductor device at high speed or to improve the reliability of the semiconductor device. In a method for manufacturing the semiconductor device, in which a gate electrode is formed over a substrate with an insulating property, a gate insulating film is formed over the gate electrode, and an oxide semiconductor film is formed over the gate insulating film, the gate insulating film is formed by deposition treatment using high-density plasma. Accordingly, dangling bonds in the gate insulating film are reduced and the quality of the interface between the gate insulating film and the oxide semiconductor is improved.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: January 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Tetsuhiro Tanaka, Seiji Yasumoto, Shun Mashiro, Yoshiaki Oikawa, Kenichi Okazaki
  • Publication number: 20140346489
    Abstract: In the case where a material containing an alkaline-earth metal in a cathode, is used, there is a fear of the diffusion of an impurity ion (such as alkaline-earth metal ion) from the EL element to the TFT being generated and causing the variation of characteristics of the TFT. Therefore, as the insulating film provided between TFT and EL element, a film containing a material for not only blocking the diffusion of an impurity ion such as an alkaline-earth metal ion but also aggressively absorbing an impurity ion such as an alkaline-earth metal ion is used.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 27, 2014
    Inventors: Satoshi MURAKAMI, Mitsuhiro ICHIJO, Taketomi ASAMI
  • Publication number: 20140332819
    Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.
    Type: Application
    Filed: July 30, 2014
    Publication date: November 13, 2014
    Inventors: Shunpei YAMAZAKI, Satoshi MURAKAMI, Motomu KURATA, Hiroyuki HATA, Mitsuhiro ICHIJO, Takashi OHTSUKI, Aya ANZAI, Masayuki SAKAKURA
  • Patent number: 8853684
    Abstract: In a transistor having a top-gate structure in which a gate electrode layer overlaps with an oxide semiconductor layer which forms a channel region with a gate insulating layer interposed therebetween, when a large amount of hydrogen is contained in the insulating layer, hydrogen is diffused into the oxide semiconductor layer because the insulating layer is in contact with the oxide semiconductor layer; thus, electric characteristics of the transistor are degraded. An object is to provide a semiconductor device having favorable electric characteristics. An insulating layer in which the concentration of hydrogen is less than 6×1020 atoms/cm3 is used for the insulating layer being in contact with oxide semiconductor layer which forms the channel region. Using the insulating layer, diffusion of hydrogen can be prevented and a semiconductor device having favorable electric characteristics can be provided.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: October 7, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda, Mizuho Sato, Mitsuhiro Ichijo, Toshiya Endo
  • Patent number: 8829527
    Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Motomu Kurata, Hiroyuki Hata, Mitsuhiro Ichijo, Takashi Ohtsuki, Aya Anzai, Masayuki Sakakura
  • Patent number: 8823009
    Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Motomu Kurata, Hiroyuki Hata, Mitsuhiro Ichijo, Takashi Ohtsuki, Aya Anzai, Masayuki Sakakura
  • Patent number: 8809203
    Abstract: It is an object to provide a method for manufacturing a semiconductor device that has a semiconductor element including a film in which mixing impurities is suppressed. It is another object to provide a method for manufacturing a semiconductor device with high yield. In a method for manufacturing a semiconductor device in which an insulating film is formed in contact with a semiconductor layer provided over a substrate having an insulating surface with use of a plasma CVD apparatus, after an inner wall of a reaction chamber of the plasma CVD apparatus is coated with a film that does not include an impurity to the insulating film, a substrate is introduced in the reaction chamber, and the insulating film is deposited over the substrate. As a result, an insulating film in which the amount of impurities is reduced can be formed.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Tetsuhiro Tanaka, Takashi Ohtsuki, Seiji Yasumoto, Kenichi Okazaki, Shunpei Yamazaki, Naoya Sakamoto
  • Patent number: 8803152
    Abstract: In the case where a material containing an alkaline-earth metal in a cathode, is used, there is a fear of the diffusion of an impurity ion (such as alkaline-earth metal ion) from the EL element to the TFT being generated and causing the variation of characteristics of the TFT. Therefore, as the insulating film provided between TFT and EL element, a film containing a material for not only blocking the diffusion of an impurity ion such as an alkaline-earth metal ion but also aggressively absorbing an impurity ion such as an alkaline-earth metal ion is used.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Mitsuhiro Ichijo, Taketomi Asami
  • Publication number: 20140027764
    Abstract: A nitride insulating film which prevents diffusion of hydrogen into an oxide semiconductor film in a transistor including an oxide semiconductor is provided. Further, a semiconductor device which has favorable electrical characteristics by using a transistor including a silicon semiconductor and a transistor including an oxide semiconductor is provided. Two nitride insulating films having different functions are provided between the transistor including a silicon semiconductor and the transistor including an oxide semiconductor. Specifically, a first nitride insulating film which contains hydrogen is provided over the transistor including a silicon semiconductor, and a second nitride insulating film which has a lower hydrogen content than the first nitride insulating film and functions as a barrier film against hydrogen is provided between the first nitride insulating film and the transistor including an oxide semiconductor.
    Type: Application
    Filed: July 22, 2013
    Publication date: January 30, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Tetsuhiro TANAKA, Yoshinori IEDA, Toshiyuki MIYAMOTO, Masafumi NOMURA, Takashi HAMOCHI, Kenichi OKAZAKI, Mitsuhiro ICHIJO, Toshiya ENDO
  • Publication number: 20140001470
    Abstract: An object is to provide a semiconductor device having good electrical characteristics. A gate insulating layer having a hydrogen concentration less than 6×1020 atoms/cm3 and a fluorine concentration greater than or equal to 1×1020 atoms/cm3 is used as a gate insulating layer in contact with an oxide semiconductor layer forming a channel region, so that the amount of hydrogen released from the gate insulating layer can be reduced and diffusion of hydrogen into the oxide semiconductor layer can be prevented. Further, hydrogen present in the oxide semiconductor layer can be eliminated with the use of fluorine; thus, the hydrogen content in the oxide semiconductor layer can be reduced. Consequently, the semiconductor device having good electrical characteristics can be provided.
    Type: Application
    Filed: September 5, 2013
    Publication date: January 2, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro ICHIJO, Toshiya ENDO, Kunihiko SUZUKI
  • Patent number: 8603899
    Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: December 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi
  • Patent number: 8592908
    Abstract: To provide a semiconductor substrate including a crystalline semiconductor layer which is suitable for practical use, even if a material different from that of the semiconductor layer is used for a supporting substrate, and a semiconductor device using the semiconductor substrate. The semiconductor substrate includes a bonding layer which forms a bonding plane, a barrier layer formed of an insulating material containing nitrogen, a relief layer which is formed of an insulating material that includes nitrogen at less than 20 at. % and hydrogen at 1 at. % to 20 at. %, and an insulating layer containing a halogen, between a supporting substrate and a single-crystal semiconductor layer. The semiconductor device includes the above-described structure at least partially, and a gate insulating layer formed by a microwave plasma CVD method using SiH4 and N2O as source gases is in contact with the single-crystal semiconductor layer.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: November 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mitsuhiro Ichijo, Makoto Furuno, Takashi Ohtsuki, Kenichi Okazaki, Tetsuhiro Tanaka, Seiji Yasumoto
  • Patent number: 8569120
    Abstract: An object is to provide a method for manufacturing a thin film transistor having favorable electric characteristics, with high productivity. A gate electrode is formed over a substrate and a gate insulating layer is formed over the gate electrode. A first semiconductor layer is formed over the gate insulating layer by generating plasma using a deposition gas containing silicon or germanium, hydrogen, and a rare gas. Next, a second semiconductor layer including an amorphous semiconductor and a microcrystal semiconductor is formed in such a manner that the first semiconductor layer is partially grown as a seed crystal by generating plasma using a deposition gas containing silicon or germanium, hydrogen, and a gas containing nitrogen. Then, a semiconductor layer to which an impurity imparting one conductivity is added is formed and a conductive film is formed. Thus, a thin film transistor is manufactured.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: October 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Erika Takahashi, Takayuki Kato, Hidekazu Miyairi, Yasuhiro Jinbo, Mitsuhiro Ichijo, Tomokazu Yokoi
  • Patent number: 8557687
    Abstract: A microcrystalline semiconductor film having a high crystallinity is formed. Further, a thin film transistor having preferable electric characteristics and high reliability and a display device including the thin film transistor are manufactured with high mass productivity. A step in which a deposition gas containing silicon or germanium is introduced at a first flow rate and a step in which the deposition gas containing silicon or germanium is introduced at a second flow rate are repeated while hydrogen is introduced at a fixed rate, so that the hydrogen and the deposition gas containing silicon or germanium are mixed, and a high-frequency power is supplied. Therefore, a microcrystalline semiconductor film is formed over a substrate.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: October 15, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryota Tajima, Tetsuhiro Tanaka, Ryo Tokumaru, Hidekazu Miyairi, Mitsuhiro Ichijo, Taichi Nozawa
  • Patent number: 8552425
    Abstract: An object is to provide a semiconductor device having good electrical characteristics. A gate insulating layer having a hydrogen concentration less than 6×1020 atoms/cm3 and a fluorine concentration greater than or equal to 1×1020 atoms/cm3 is used as a gate insulating layer in contact with an oxide semiconductor layer forming a channel region, so that the amount of hydrogen released from the gate insulating layer can be reduced and diffusion of hydrogen into the oxide semiconductor layer can be prevented. Further, hydrogen present in the oxide semiconductor layer can be eliminated with the use of fluorine; thus, the hydrogen content in the oxide semiconductor layer can be reduced. Consequently, the semiconductor device having good electrical characteristics can be provided.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: October 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Toshiya Endo, Kunihiko Suzuki