Patents by Inventor Mitsuhiro Ichijo

Mitsuhiro Ichijo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130228784
    Abstract: In the case where a material containing an alkaline-earth metal in a cathode, is used, there is a fear of the diffusion of an impurity ion (such as alkaline-earth metal ion) from the EL element to the TFT being generated and causing the variation of characteristics of the TFT. Therefore, as the insulating film provided between TFT and EL element, a film containing a material for not only blocking the diffusion of an impurity ion such as an alkaline-earth metal ion but also aggressively absorbing an impurity ion such as an alkaline-earth metal ion is used.
    Type: Application
    Filed: April 18, 2013
    Publication date: September 5, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi MURAKAMI, Mitsuhiro ICHIJO, Taketomi ASAMI
  • Patent number: 8486777
    Abstract: A technique for manufacturing a microcrystalline semiconductor layer with high mass productivity is provided. In a reaction chamber of a plasma CVD apparatus, an upper electrode and a lower electrode are provided in almost parallel to each other. A hollow portion is formed in the upper electrode, and the upper electrode includes a shower plate having a plurality of holes formed on a surface of the upper electrode which faces the lower electrode. A substrate is provided over the lower electrode. A gas containing a deposition gas and hydrogen is supplied to the reaction chamber from the shower plate through the hollow portion of the upper electrode, and a rare gas is supplied to the reaction chamber from a portion different from the upper electrode. Accordingly, high-frequency power is supplied to the upper electrode to generate plasma, so that a microcrystalline semiconductor layer is formed over the substrate.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: July 16, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Kazutaka Kuriki, Tomokazu Yokoi, Toshiya Endo
  • Patent number: 8476638
    Abstract: An object of the present invention is to provide a technique for manufacturing a dense crystalline semiconductor film without a cavity between crystal grains. A plasma region is formed between a first electrode and a second electrode by supplying high-frequency power of 60 MHz or less to the first electrode under a condition where a pressure of a reactive gas in a reaction chamber of a plasma CVD apparatus is set to 450 Pa to 13332 Pa, and a distance between the first electrode and the second electrode of the plasma CVD apparatus is set to 1 mm to 20 mm; crystalline deposition precursors are formed in a gas phase including the plasma region; a crystal nucleus of 5 nm to 15 nm is formed by depositing the deposition precursors; and a microcrystalline semiconductor film is formed by growing a crystal from the crystal nucleus.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: July 2, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Toriumi, Ryota Tajima, Takashi Ohtsuki, Tetsuhiro Tanaka, Ryo Tokumaru, Mitsuhiro Ichijo, Kazutaka Kuriki, Tomokazu Yokoi, Toshiya Endo, Shunpei Yamazaki
  • Patent number: 8450741
    Abstract: In the case where a material containing an alkaline-earth metal in a cathode, is used, there is a fear of the diffusion of an impurity ion (such as alkaline-earth metal ion) from the EL element to the TFT being generated and causing the variation of characteristics of the TFT. Therefore, as the insulating film provided between TFT and EL element, a film containing a material for not only blocking the diffusion of an impurity ion such as an alkaline-earth metal ion but also aggressively absorbing an impurity ion such as an alkaline-earth metal ion is used.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: May 28, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Mitsuhiro Ichijo, Taketomi Asami
  • Patent number: 8441010
    Abstract: In a transistor including an oxide semiconductor, hydrogen in the oxide semiconductor leads to degradation of electric characteristics of the transistor. Thus, an object is to provide a semiconductor device having good electrical characteristics. An insulating layer in contact with an oxide semiconductor layer where a channel region is formed is formed by a plasma CVD method using a silicon halide. The insulating layer thus formed has a hydrogen concentration less than 6×1020 atoms/cm3 and a halogen concentration greater than or equal to 1×1020 atoms/cm3; accordingly, hydrogen diffusion into the oxide semiconductor layer can be prevented and hydrogen in the oxide semiconductor layer is inactivated or released from the oxide semiconductor layer by the halogen, whereby a semiconductor device having good electrical characteristics can be provided.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: May 14, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Toshiya Endo, Kunihiko Suzuki, Yasuhiko Takemura
  • Publication number: 20130001571
    Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 3, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Satoshi MURAKAMI, Motomu KURATA, Hiroyuki HATA, Mitsuhiro ICHIJO, Takashi OHTSUKI, Aya ANZAI, Masayuki SAKAKURA
  • Patent number: 8344378
    Abstract: An object is to provide a thin film transistor with small off current, large on current, and high field-effect mobility. A silicon nitride layer and a silicon oxide layer which is formed by oxidizing the silicon nitride layer are stacked as a gate insulating layer, and crystals grow from an interface of the silicon oxide layer of the gate insulating layer to form a microcrystalline semiconductor layer; thus, an inverted staggered thin film transistor is manufactured. Since crystals grow from the gate insulating layer, the thin film transistor can have a high crystallinity, large on current, and high field-effect mobility. In addition, a buffer layer is provided to reduce off current.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Miyako Nakajima, Hidekazu Miyairi, Toshiyuki Isa, Erika Kato, Mitsuhiro Ichijo, Kazutaka Kuriki, Tomokazu Yokoi
  • Publication number: 20120304932
    Abstract: An object of the present invention is to provide a technique for manufacturing a dense crystalline semiconductor film without a cavity between crystal grains. A plasma region is formed between a first electrode and a second electrode by supplying high-frequency power of 60 MHz or less to the first electrode under a condition where a pressure of a reactive gas in a reaction chamber of a plasma CVD apparatus is set to 450 Pa to 13332 Pa, and a distance between the first electrode and the second electrode of the plasma CVD apparatus is set to 1 mm to 20 mm; crystalline deposition precursors are formed in a gas phase including the plasma region; a crystal nucleus of 5 nm to 15 nm is formed by depositing the deposition precursors; and a microcrystalline semiconductor film is formed by growing a crystal from the crystal nucleus.
    Type: Application
    Filed: July 17, 2012
    Publication date: December 6, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Satoshi Toriumi, Ryota Tajima, Takashi Ohtsuki, Tetsuhiro Tanaka, Ryo Tokumaru, Mitsuhiro Ichijo, Kazutaka Kuriki, Tomokazu Yokoi, Toshiya Endo, Shunpei Yamazaki
  • Patent number: 8324699
    Abstract: A method for manufacturing an insulating film, which is used as an insulating film used for a semiconductor integrated circuit, whose reliability can be ensured even though it has small thickness, is provided. In particular, a method for manufacturing a high-quality insulating film over a substrate having an insulating surface, which can be enlarged, at low substrate temperature, is provided. A monosilane gas (SiH4), nitrous oxide (N2O), and a rare gas are introduced into a chamber to generate high-density plasma at a pressure higher than or equal to 10 Pa and lower than or equal to 30 Pa so that an insulating film is formed over a substrate having an insulating surface. After that, the supply of a monosilane gas is stopped, and nitrous oxide (N2O) and a rare gas are introduced without exposure to the air to perform plasma treatment on a surface of the insulating film.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Kenichi Okazaki, Tetsuhiro Tanaka, Takashi Ohtsuki, Seiji Yasumoto, Shunpei Yamazaki
  • Patent number: 8304327
    Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: November 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi
  • Patent number: 8300168
    Abstract: It is an object to provide a manufacturing method by which display devices can be manufactured in quantity without degrading the characteristics of thin film transistors. In a display device including a thin film transistor in which a microcrystalline semiconductor film, a gate insulating film in contact with the microcrystalline semiconductor film, and a gate electrode overlap with each other, an antioxidant film is formed on a surface of the microcrystalline semiconductor film. The antioxidant film on the surface of the microcrystalline semiconductor film can prevent a surface of a microcrystal grain from being oxidized, thereby preventing the mobility of the thin film transistor from decreasing.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: October 30, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mitsuhiro Ichijo, Tetsuhiro Tanaka, Takashi Ohtsuki, Seiji Yasumoto, Kenichi Okazaki
  • Publication number: 20120248470
    Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.
    Type: Application
    Filed: June 1, 2012
    Publication date: October 4, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Satoshi MURAKAMI, Motomu KURATA, Hiroyuki HATA, Mitsuhiro ICHIJO, Takashi OHTSUKI, Aya ANZAI, Masayuki SAKAKURA
  • Patent number: 8252669
    Abstract: An object of one embodiment of the present invention is to provide a technique for manufacturing a dense crystalline semiconductor film (e.g., a microcrystalline semiconductor film) without a cavity between crystal grains. A plasma region is formed between a first electrode and a second electrode by supplying high-frequency power of 60 MHz or less to the first electrode under a condition where a pressure of a reactive gas in a reaction chamber of a plasma CVD apparatus is set to 450 Pa to 13332 Pa, and a distance between the first electrode and the second electrode of the plasma CVD apparatus is set to 1 mm to 20 mm; crystalline deposition precursors are formed in a gas phase including the plasma region; a crystal nucleus of 5 nm to 15 nm is formed by depositing the deposition precursors; and a microcrystalline semiconductor film is formed by growing a crystal from the crystal nucleus.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: August 28, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Toriumi, Ryota Tajima, Takashi Ohtsuki, Tetsuhiro Tanaka, Ryo Tokumaru, Mitsuhiro Ichijo, Kazutaka Kuriki, Tomokazu Yokoi, Toshiya Endo, Shunpei Yamazaki
  • Patent number: 8247315
    Abstract: By an evacuation unit including first and second turbo molecular pumps connected in series, the ultimate pressure in a reaction chamber is reduced to ultra-high vacuum. By a knife-edge-type metal-seal flange, the amount of leakage in the reaction chamber is reduced. A microcrystalline semiconductor film and an amorphous semiconductor film are stacked in the same reaction chamber where the pressure is reduced to ultra-high vacuum. By forming the amorphous semiconductor film covering the surface of the microcrystalline semiconductor film, oxidation of the microcrystalline semiconductor film is prevented.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: August 21, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Makoto Furuno, Tetsuo Sugiyama, Taichi Nozawa, Mitsuhiro Ichijo, Ryota Tajima, Shunpei Yamazaki
  • Patent number: 8217396
    Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: July 10, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Motomu Kurata, Hiroyuki Hata, Mitsuhiro Ichijo, Takashi Ohtsuki, Aya Anzai, Masayuki Sakakura
  • Publication number: 20120156556
    Abstract: An electrode in which a silicon layer is provided over a current collector, a thin film layer having a thickness within a certain range is provided on a surface of the silicon layer, and the thin film layer contains fluorine, is used for a power storage device. The thickness of the thin film layer containing fluorine is greater than 0 nm and less than or equal to 10 nm, preferably greater than or equal to 4 nm and less than or equal to 9 nm. The fluorine concentration of the thin film layer containing fluorine is preferably as high as possible, and the nitrogen concentration, the oxygen concentration, and the hydrogen concentration thereof are preferably as low as possible.
    Type: Application
    Filed: November 30, 2011
    Publication date: June 21, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazutaka KURIKI, Mitsuhiro Ichijo, Toshiya Endo
  • Publication number: 20120129329
    Abstract: The present invention is provided in order to remove contamination due to contaminant impurities of the interfaces of each film which forms a TFT, which is the major factor that reduces the reliability of TFTs. By connecting a washing chamber and a film formation chamber, film formation can be carried out without exposing TFTs to the air during the time from washing step to the film formation step and it becomes possible to maintain the cleanliness of the interfaces of each film which form the TFT.
    Type: Application
    Filed: January 31, 2012
    Publication date: May 24, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Taketomi ASAMI, Mitsuhiro ICHIJO, Satoshi TORIUMI, Takashi OHTSUKI, Shunpei YAMAZAKI
  • Publication number: 20120100677
    Abstract: A technique for manufacturing a microcrystalline semiconductor layer with high mass productivity is provided. In a reaction chamber of a plasma CVD apparatus, an upper electrode and a lower electrode are provided in almost parallel to each other. A hollow portion is formed in the upper electrode, and the upper electrode includes a shower plate having a plurality of holes formed on a surface of the upper electrode which faces the lower electrode. A substrate is provided over the lower electrode. A gas containing a deposition gas and hydrogen is supplied to the reaction chamber from the shower plate through the hollow portion of the upper electrode, and a rare gas is supplied to the reaction chamber from a portion different from the upper electrode. Accordingly, high-frequency power is supplied to the upper electrode to generate plasma, so that a microcrystalline semiconductor layer is formed over the substrate.
    Type: Application
    Filed: January 5, 2012
    Publication date: April 26, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Mitsuhiro ICHIJO, Kazutaka KURIKI, Tomokazu YOKOI, Toshiya ENDO
  • Publication number: 20120100309
    Abstract: A plasma treatment apparatus includes a treatment chamber covered with a chamber wall, where an upper electrode faces a lower electrode; and a line chamber separated from the treatment chamber by the upper electrode and an insulator, covered with the chamber wall, and connected to a first gas diffusion chamber between a dispersion plate and a shower plate. The first gas diffusion chamber is connected to a second gas diffusion chamber between the dispersion plate and the upper electrode. The second gas diffusion chamber is connected to a first gas pipe in the upper electrode. The upper electrode and the chamber wall are provided on the same axis. The dispersion plate includes a center portion with no gas hole and a peripheral portion with plural gas holes. The center portion faces a gas introduction port of the first gas pipe, connected to an electrode plane of the upper electrode.
    Type: Application
    Filed: October 14, 2011
    Publication date: April 26, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hidekazu MIYAIRI, Yoichiro NUMASAWA, Takayuki INOUE, Kojiro TAKAHASHI, Mitsuhiro ICHIJO
  • Patent number: 8138101
    Abstract: The present invention is provided in order to remove contamination due to contaminant impurities of the interfaces of each film which forms a TFT, which is the major factor that reduces the reliability of TFTs. By connecting a washing chamber and a film formation chamber, film formation can be carried out without exposing TFTs to the air during the time from washing step to the film formation step and it becomes possible to maintain the cleanliness of the interfaces of each film which form the TFT.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: March 20, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Shunpei Yamazaki