Abstract: According to one embodiment, a memory system includes a storage unit with a plurality of pages of a plurality of nonvolatile memory cells, each page having a lower page unit and a higher page unit. A correction processing unit for correcting errors in the data stored in the storage unit on a page-by-page basis is provided. A controller is further configured to track a storage location of multi-level data in the storage unit, detect pages for which data is stored only in the lower page unit, cause the correction processing unit to generate an error correction code for the detected page units in an encoding frame, and write the error correction code to a next page unit among the plurality of pages in a set writing order after the last lower page unit in the encoding frame.

Abstract: A memory system according to an embodiment includes a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks. The memory controller includes first and second tables, and first and second storage areas. The first table is managed in units of map segments. The second table includes first entries associated with a plurality of map segments included in the first table. The first storage area is configured to store a change history of the first table. The second storage area is configured to store a physical address of a block that is a storage destination of a copy of a changed map segment and a change history of the second table.

Abstract: A controller assigns, for each namespace, one logical area of a logical address space as a first logical area including a last logical address of the namespace and assigns one or more of logical areas as second logical areas. The controller divides a memory region in which an address translation table is stored into buffer regions. For each second logical area, the controller assigns one buffer region for storing map segments corresponding to the second logical area, and manages a first pointer indicating a storage location of the buffer region assigned thereto. The controller also assigns one buffer region for map segments corresponding to the first logical areas of two or more namespaces, and manages second pointers respectively indicating storage locations in the one buffer region, in which the map segments corresponding to the first logical areas of the two or more namespaces are respectively stored.

Abstract: According to an embodiment, when receiving a read request designating a logical address range of a particular size or more from a host, a first circuit issues a plurality of first sub-commands, each of which is a sub-command for each first data unit, in order of logical addresses. A second circuit respectively adds serial numbers corresponding to the plurality of first sub-commands in the order of issuance. A plurality of third circuits respectively executes processing of specifying locations of the first data unit based on management information for the plurality of first sub-commands in a distributed manner. A fifth circuit reorders the plurality of first sub-commands in the logical address order based on the serial numbers after the processing by the plurality of third circuits. A sixth circuit executes a read operation on a first memory based on the plurality of first sub-commands reordered in the order of logical addresses.

Abstract: A storage device includes a nonvolatile memory, a volatile memory, and a controller accesses the nonvolatile memory using an address conversion table including regions, each region including entries, each entry storing a physical address of the nonvolatile memory in association with a logical address, and reads and writes data of the address conversion table from and to the nonvolatile memory and the volatile memory in a unit of a frame. The controller writes, to the nonvolatile memory, data of a first region in a first format in which a head address of data of a region aligns with a head address of a frame, and writes, to the volatile memory, data of a second region in either the first format or a second format in which a head address of data of a region does not align with a head address of a frame.

Abstract: A memory system includes a memory controller and a first number of memory elements connected to the memory controller via one or more channels. The memory controller includes a second number of polling circuits and a first processor. Each polling circuit receives designation of one memory element out of the first number of memory elements and executes a polling operation. The polling operation is an operation to repeat an inquiry to the designated memory element until detecting that a status of the designated memory element is a ready status. The first processor selects a polling circuit that is not executing the polling operation among the second number of polling circuits. The first processor designates, for the selected polling circuit, one memory element out of the first number of memory elements and causes the selected polling circuit to execute the polling operation on the designated one memory element.

Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.

Abstract: A memory system includes a non-volatile memory including first and second chips, a processor configured to generate first messages in response to a command from an external device, the first messages addressed to the first and second chips, and a repeater including an input port to which the first messages are input and first and second output ports connected to the first and second chips. The repeater is configured to write the first messages input via the input port to a shared memory, read the first message addressed to the first chip from the shared memory when the first chip is ready, and output the first message to the first chip through the first output port, and read the first message addressed to the second chip when the second chip is ready, and output the second message to the second chip through the second output port.

Abstract: According to an embodiment, when receiving a read request designating a logical address range of a particular size or more from a host, a first circuit issues a plurality of first sub-commands, each of which is a sub-command for each first data unit, in order of logical addresses. A second circuit respectively adds serial numbers corresponding to the plurality of first sub-commands in the order of issuance. A plurality of third circuits respectively executes processing of specifying locations of the first data unit based on management information for the plurality of first sub-commands in a distributed manner. A fifth circuit reorders the plurality of first sub-commands in the logical address order based on the serial numbers after the processing by the plurality of third circuits. A sixth circuit executes a read operation on a first memory based on the plurality of first sub-commands reordered in the order of logical addresses.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller manages memory area sets. The controller distributes a first memory area set into a first group. The controller distributes a second memory area set into a second group. The controller comprises first to fourth circuits. The first circuit processes a first read request from a host to the first memory area set. The second circuit processes a first write request from the host to the first memory area set. The third circuit processes a second read request from the host to the second memory area set. The fourth circuit processes a second write request from the host to the second memory area set.

Abstract: A memory system includes a non-volatile memory including first and second memory chips connected to a channel, each chip outputting a first signal indicating whether the chip is in a busy state, a first queue storing commands to be executed by the first chip, a second queue storing commands to be executed by the second chip, a processor configured to issue a second signal indicating whether a command in the first or second queue is a first-type or a second-type command, the first-type command causing the first or second chip to be in the busy state longer than the second-type command, a first arbiter selecting from the first and second queues a command to be executed next based on the first and second signals, and an interface controller sending the selected command via the channel to the first or second memory chip.

Abstract: A storage device includes a nonvolatile memory, a volatile memory, and a controller accesses the nonvolatile memory using an address conversion table including regions, each region including entries, each entry storing a physical address of the nonvolatile memory in association with a logical address, and reads and writes data of the address conversion table from and to the nonvolatile memory and the volatile memory in a unit of a frame. The controller writes, to the nonvolatile memory, data of a first region in a first format in which a head address of data of a region aligns with a head address of a frame, and writes, to the volatile memory, data of a second region in either the first format or a second format in which a head address of data of a region does not align with a head address of a frame.

Abstract: A memory system according to an embodiment includes a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks. The memory controller includes first and second tables, and first and second storage areas. The first table is managed in units of map segments. The second table includes first entries associated with a plurality of map segments included in the first table. The first storage area is configured to store a change history of the first table. The second storage area is configured to store a physical address of a block that is a storage destination of a copy of a changed map segment and a change history of the second table.

Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.

Abstract: A storage device includes a nonvolatile memory, a volatile memory, and a controller accesses the nonvolatile memory using an address conversion table including regions, each region including entries, each entry storing a physical address of the nonvolatile memory in association with a logical address, and reads and writes data of the address conversion table from and to the nonvolatile memory and the volatile memory in a unit of a frame. The controller writes, to the nonvolatile memory, data of a first region in a first format in which a head address of data of a region aligns with a head address of a frame, and writes, to the volatile memory, data of a second region in either the first format or a second format in which a head address of data of a region does not align with a head address of a frame.

Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.

Abstract: A memory system is connectable to the host. The memory system includes a nonvolatile first memory, a second memory in which a plurality of pieces of first information each correlating a logical address indicating a location in a logical address space of the memory system with a physical address indicating a location in the first memory are stored, a volatile third memory including a first cache and a second cache, a compressor configured to perform compression on the plurality of pieces of first information, and a memory controller. The memory controller stores the first information not compressed by the compressor in the first cache, stores the first information compressed by the compressor in the second cache, and controls a ratio between a first capacity, which is a capacity of the first cache, and a second capacity, which is a capacity of the second cache.

Abstract: A memory system according to an embodiment includes a first memory, a second memory, and a controller. The first memory stores first information that associates each of logical addresses indicating positions in a logical address space with a corresponding one of physical addresses indicating physical positions in the first memory. The second memory includes a cache area storing second information that is a part of the first information. The controller includes a first circuit controlling access to the first memory and a second circuit controlling access to the second memory. When cache miss occurs, the controller executes first processing of transmitting a first request for preparation of a cache entry of the second information to the first circuit and second processing of providing a second request regarding the cache entry to the second circuit in response to reception of notification indicating completion of the preparation of the cache entry.

Abstract: According to one embodiment, a memory apparatus includes a memory device and a controller. The memory device includes a plurality of memory chips. The controller includes a plurality of memories. The controller determines whether or not the memory chip is allocated to any one memory when receiving an access request related to the memory chip from a host apparatus. The controller newly allocates the memory chip to the memory to which none of the memory chips is allocated when it is determined that the memory chips is not allocated, and enqueues a command corresponding to the access request received from the host apparatus to the memory to which the memory chip is newly allocated.

Abstract: A multiprocessor system includes a shared memory, and first and second processors. The shared memory includes a queue configured to store messages. The first processor transmits the messages to the shared memory. The second processor receives the messages stored in the shared memory. The first memory stores a first head pointer indicating a vacant position head of the queue and a first tail pointer indicating a vacant position tail of the queue. The second memory stores a second head pointer indicating a position of a head of the messages stored in the queue and a second tail pointer indicating a tail position of the messages stored in the queue. The first processor increments the first head pointer and copies a value identical to a value of the first head pointer to the second tail pointer, when transmitting the messages.