Patents by Inventor Mitsunori Tadokoro

Mitsunori Tadokoro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140298448
    Abstract: According to one embodiment, a storage device that has a nonvolatile semiconductor memory includes an authentication information storage unit that previously stores first apparatus authentication information to authenticate an authorized host device and first user authentication information to authenticate an authorized user. The storage device executes apparatus authentication on the basis of second apparatus authentication information received from a newly connected host device and the first apparatus authentication information in the authentication information storage unit and executes an invalidation process of user data stored in the nonvolatile semiconductor memory, when the apparatus authentication is failed.
    Type: Application
    Filed: June 11, 2014
    Publication date: October 2, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nagai, Mitsunori Tadokoro, Teruji Yamakawa, Kazuo Nakashima
  • Publication number: 20140258675
    Abstract: A memory controller according to the embodiment includes a front-end unit that issues an invalidation command in response to a command from outside of the memory controller, the command including a logical address, an address translation unit that stores a correspondence relationship between the logical and a physical address, an invalidation command processing unit that, when the invalidation command is received, registers the logical address associated with the invalidation command as an invalidation registration region in an invalidation registration unit and issues a notification to the front-end unit, and an internal processing unit that dissolves a correspondence relationship between the logical address registered in the invalidation registration unit and the physical address in the address translation unit in a predetermined order by referencing the logical address registered in the invalidation registration unit.
    Type: Application
    Filed: September 10, 2013
    Publication date: September 11, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki TAKEUCHI, Yoshihisa Kojima, Norio Aoyama, Mitsunori Tadokoro
  • Patent number: 8825946
    Abstract: According to one embodiment, when a controller writes update data in a second memory to a first memory which is nonvolatile and a difference between a size of a page and a size of the update data is equal to or greater than a size of a cluster, the controller configured to generate write data by adding, to the update data, data which has the size of the cluster, store an update content of management information corresponding to the update data and an update content storage position indicating a storage position of the update content of the management information in the first memory, and write the generated write data to a block in writing of the first memory.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryoichi Kato, Mitsunori Tadokoro, Takashi Hirao
  • Publication number: 20140244903
    Abstract: According to one embodiment, a memory controller includes a mode selection part that selects one of a MLC-mode and a SLC-mode, after a write command is decoded by a command decode part, and a write part that executes a data writing to a storage memory by using one of the MLC-mode and the SLC-mode selected by the mode selection part. The mode selection part is configured to check whether a first data wrote from a host to a buffer memory is a time-continuous data that is wrote continuously during a predetermined period, execute the data writing of a second data from the buffer memory to the storage memory in the MLC-mode, when the first data is the time-continuous data, and execute the data writing of the second data from the buffer memory to the storage memory in the SLC-mode, when the first data is not the time-continuous data.
    Type: Application
    Filed: June 5, 2013
    Publication date: August 28, 2014
    Inventors: Hirokuni YANO, Mitsunori TADOKORO
  • Patent number: 8782804
    Abstract: According to one embodiment, a storage device that has a nonvolatile semiconductor memory includes an authentication information storage unit that previously stores first apparatus authentication information to authenticate an authorized host device and first user authentication information to authenticate an authorized user. The storage device executes apparatus authentication on the basis of second apparatus authentication information received from a newly connected host device and the first apparatus authentication information in the authentication information storage unit and executes an invalidation process of user data stored in the nonvolatile semiconductor memory, when the apparatus authentication is failed.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nagai, Mitsunori Tadokoro, Teruji Yamakawa, Kazuo Nakashima
  • Patent number: 8745443
    Abstract: According to one embodiment, a memory system includes a data manager and a data restorer. The data manager multiplexes difference logs by a parallel writing operation and stores them in a second storage area, the difference logs being difference logs indicating difference information before and after update of a management table; and thereafter multiplexes predetermined data as finalizing logs and stores them in the second storage area. The data restorer determines a system status at startup of the memory system, by judging whether irregular power-off occurs or data destruction occurs in the second storage area, based on a data storage state of the difference logs and the finalizing logs stored in the second storage area.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Hirao, Mitsunori Tadokoro, Hirokuni Yano
  • Publication number: 20140040650
    Abstract: According to one embodiment, a semiconductor storage device includes a nonvolatile memory, memory controller storing control information, a switch between the nonvolatile memory/memory controller and a power supply terminal, a second memory, an interpreter interprets a command, a switch controller, and a third memory stores an address of the control information in the second memory. The memory controller instructs the switch controller to open the switch after writing the control information into the second memory and reads the control information from the second memory based on the address stored in the third memory when the memory controller is electrically connected to the first power supply terminal.
    Type: Application
    Filed: December 27, 2012
    Publication date: February 6, 2014
    Inventors: Toshikatsu HIDA, Mitsunori TADOKORO
  • Publication number: 20130246716
    Abstract: According to one embodiment, when a controller writes update data in a second memory to a first memory which is nonvolatile and a difference between a size of a page and a size of the update data is equal to or greater than a size of a cluster, the controller configured to generate write data by adding, to the update data, data which has the size of the cluster, store an update content of management information corresponding to the update data and an update content storage position indicating a storage position of the update content of the management information in the first memory, and write the generated write data to a block in writing of the first memory.
    Type: Application
    Filed: September 14, 2012
    Publication date: September 19, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ryoichi KATO, Mitsunori Tadokoro, Takashi Hirao
  • Publication number: 20130232296
    Abstract: A memory system in embodiments includes a nonvolatile semiconductor memory that stores user data, a forward lookup address translation table and a reverse lookup address translation table, and a controller. The controller is configured to determine that the user data stored in the nonvolatile semiconductor memory is valid or invalid based on these two tables. The controller may perform data organizing of selecting data determined valid and rewriting the data in a new block. The controller may perform write processing and rewriting processing to the new block alternately at a predetermined ratio. The controller may determine whether a predetermined condition is satisfied on a basis of addresses included in write requests and write data in the MLC mode when the condition is satisfied and write data in the SLC mode when the condition is not satisfied.
    Type: Application
    Filed: August 30, 2012
    Publication date: September 5, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinji YONEZAWA, Takashi HIRAO, Hirokuni YANO, Mitsunori TADOKORO, Hiroki MATSUDAIRA, Akira SAWAOKA
  • Publication number: 20130227246
    Abstract: A management information generating method wherein logical and physical block addresses (BAs) of continuous addresses are associated with each other in the BA translation table. When a logical block is constructed, an allowable value is set for the number of defective physical blocks. A logical block having fewer defects than the set number is set usable, and a logical block having more defects than the set number is set unusable. System logical block construction is performed to preferentially select physical blocks from a plane list including a large number of usable blocks to equalize the number of usable blocks in each plane list. It is determined whether the number of free blocks is insufficient on the basis of a first management unit and whether the storage area for the indicated capacity can be reserved on the basis of the management unit different from the first unit.
    Type: Application
    Filed: September 11, 2012
    Publication date: August 29, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi HIRAO, Hirokuni YANO, Aurelien Nam Phong TRAN, Mitsunori TADOKORO, Hiroki MATSUDAIRA, Tatsuya SUMIYOSHI, Yoshimi NIISATO, Kenji TANAKA
  • Publication number: 20120260023
    Abstract: According to one embodiment, a storage device includes, when power is supplied to a storage unit, counting of an elapsed time is started. If a command is input from a host device, and the elapsed time from input of a previous command to input of a current command is calculated based on time information clocked by the host device and on a counter value counted until the corresponding command is input. Matching of the time information is determined based on a temporal relation between the adding result of adding the calculated elapsed time to the time information included in the previous command and the time information included in the current command. When the mismatching is determined, data in the storage unit is invalidated.
    Type: Application
    Filed: September 23, 2011
    Publication date: October 11, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi NAGAI, Mitsunori Tadokoro, Teruji Yamakawa, Kazuo Nakashima
  • Publication number: 20120260349
    Abstract: According to one embodiment, a storage device that has a nonvolatile semiconductor memory includes an authentication information storage unit that previously stores first apparatus authentication information to authenticate an authorized host device and first user authentication information to authenticate an authorized user. The storage device executes apparatus authentication on the basis of second apparatus authentication information received from a newly connected host device and the first apparatus authentication information in the authentication information storage unit and executes an invalidation process of user data stored in the nonvolatile semiconductor memory, when the apparatus authentication is failed.
    Type: Application
    Filed: February 29, 2012
    Publication date: October 11, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nagai, Mitsunori Tadokoro, Teruji Yamakawa, Kazuo Nakashima
  • Publication number: 20120159244
    Abstract: According to one embodiment, a memory system includes a data manager and a data restorer. The data manager multiplexes difference logs by a parallel writing operation and stores them in a second storage area, the difference logs being difference logs indicating difference information before and after update of a management table; and thereafter multiplexes predetermined data as finalizing logs and stores them in the second storage area. The data restorer determines a system status at startup of the memory system, by judging whether irregular power-off occurs or data destruction occurs in the second storage area, based on a data storage state of the difference logs and the finalizing logs stored in the second storage area.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 21, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi HIRAO, Mitsunori TADOKORO, Hirokuni YANO
  • Publication number: 20070016719
    Abstract: A memory device includes a first nonvolatile memory and a second nonvolatile memory. The first nonvolatile memory is used as a main memory and includes a plurality of physical blocks which store data. The second nonvolatile memory is used as a cache memory for the first nonvolatile memory and includes a plurality of block entries which store data and an information table in which cache management information used to allow the second nonvolatile memory to operate as the cache memory is stored.
    Type: Application
    Filed: April 8, 2005
    Publication date: January 18, 2007
    Inventors: Nobuhiro Ono, Ayako Tsuji, Mitsunori Tadokoro