Abstract: A memory system has a non-volatile memory having a plurality of memory cells, and a controller configured to control writing, reading, and erasing of data into and from the non-volatile memory. The non-volatile memory includes a page for which the data is written and read to and from at least a part of the plurality of memory cells, and a block having a plurality of the pages. The controller manages a first block group including a plurality of the blocks and a second block group including a plurality of the first block groups, and generates a first parity for correcting an error occurring in the second block group by data in each of the plurality of first block groups in the second block group, and a second parity for correcting an error occurring in the first block group by data in the first block group.

Abstract: According to one embodiment, a memory system allocates one or more areas of a plurality of areas obtained by equally dividing a first logical address space of the memory system to each of a plurality of namespaces. Each of the areas has such a size that areas corresponding in number to a maximum number of namespaces to be supported are allocable to a remaining space excluding a size equivalent to that of an advertised capacity form the first logical address space. When a size of a first namespace is to be expanded, the memory system updates the first management table and additionally allocates an unused area to the first namespace.

Abstract: A storage apparatus includes a storage device that stores a table mapping a logical address to a physical address and a controller that manages the table and controls write of data to and read of data from the storage device according to a request from a host. The controller allocates, in a memory, a cache area for temporarily storing a part of the table, and a write buffer area for storing a part of the table that has been updated by the host and is to be written to the storage device, upon receipt of a request that requires update of the table from the host, determines whether a first part of the table to be updated is in the write buffer area, and upon determining that the first part is in the write buffer area, updates the first part in the write buffer area according to the request.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller manages memory area sets. The controller distributes a first memory area set into a first group. The controller distributes a second memory area set into a second group. The controller comprises first to fourth circuits. The first circuit processes a first read request from a host to the first memory area set. The second circuit processes a first write request from the host to the first memory area set. The third circuit processes a second read request from the host to the second memory area set. The fourth circuit processes a second write request from the host to the second memory area set.

Abstract: A memory system has a non-volatile memory having a plurality of memory cells, and a controller configured to control writing, reading, and erasing of data into and from the non-volatile memory. The non-volatile memory includes a page for which the data is written and read to and from at least a part of the plurality of memory cells, and a block having a plurality of the pages. The controller manages a first block group including a plurality of the blocks and a second block group including a plurality of the first block groups, and generates a first parity for correcting an error occurring in the second block group by data in each of the plurality of first block groups in the second block group, and a second parity for correcting an error occurring in the first block group by data in the first block group.

Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.

Abstract: A storage apparatus includes a storage device that stores a table mapping a logical address to a physical address and a controller that manages the table and controls write of data to and read of data from the storage device according to a request from a host. The controller allocates, in a memory, a cache area for temporarily storing a part of the table, and a write buffer area for storing a part of the table that has been updated by the host and is to be written to the storage device, upon receipt of a request that requires update of the table from the host, determines whether a first part of the table to be updated is in the write buffer area, and upon determining that the first part is in the write buffer area, updates the first part in the write buffer area according to the request.

Abstract: According to one embodiment, a memory system allocates one or more areas of a plurality of areas obtained by equally dividing a first logical address space of the memory system to each of a plurality of namespaces. Each of the areas has such a size that areas corresponding in number to a maximum number of namespaces to be supported are allocable to a remaining space excluding a size equivalent to that of an advertised capacity form the first logical address space. When a size of a first namespace is to be expanded, the memory system updates the first management table and additionally allocates an unused area to the first namespace.

Abstract: A storage device includes a nonvolatile memory, a volatile memory, and a controller accesses the nonvolatile memory using an address conversion table including regions, each region including entries, each entry storing a physical address of the nonvolatile memory in association with a logical address, and reads and writes data of the address conversion table from and to the nonvolatile memory and the volatile memory in a unit of a frame. The controller writes, to the nonvolatile memory, data of a first region in a first format in which a head address of data of a region aligns with a head address of a frame, and writes, to the volatile memory, data of a second region in either the first format or a second format in which a head address of data of a region does not align with a head address of a frame.

Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.

Abstract: A memory system is connectable to the host. The memory system includes a nonvolatile first memory, a second memory in which a plurality of pieces of first information each correlating a logical address indicating a location in a logical address space of the memory system with a physical address indicating a location in the first memory are stored, a volatile third memory including a first cache and a second cache, a compressor configured to perform compression on the plurality of pieces of first information, and a memory controller. The memory controller stores the first information not compressed by the compressor in the first cache, stores the first information compressed by the compressor in the second cache, and controls a ratio between a first capacity, which is a capacity of the first cache, and a second capacity, which is a capacity of the second cache.

Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.

Abstract: A multiprocessor system includes a shared memory, and first and second processors. The shared memory includes a queue configured to store messages. The first processor transmits the messages to the shared memory. The second processor receives the messages stored in the shared memory. The first memory stores a first head pointer indicating a vacant position head of the queue and a first tail pointer indicating a vacant position tail of the queue. The second memory stores a second head pointer indicating a position of a head of the messages stored in the queue and a second tail pointer indicating a tail position of the messages stored in the queue. The first processor increments the first head pointer and copies a value identical to a value of the first head pointer to the second tail pointer, when transmitting the messages.

Abstract: According to one embodiment, a memory apparatus includes a memory device and a controller. The memory device includes a plurality of memory chips. The controller includes a plurality of memories. The controller determines whether or not the memory chip is allocated to any one memory when receiving an access request related to the memory chip from a host apparatus. The controller newly allocates the memory chip to the memory to which none of the memory chips is allocated when it is determined that the memory chips is not allocated, and enqueues a command corresponding to the access request received from the host apparatus to the memory to which the memory chip is newly allocated.

Abstract: A memory system includes: a non-volatile first memory; a second memory which is a set-associative cache memory including a plurality of ways; and a memory controller The first memory stores a plurality of pieces of first information each of which associates a logical address indicating a location in a logical address space of the memory system with a physical address indicating a location in the first memory. The plurality of pieces of first information includes second information and third information. The second information associates a logical address with a physical address in a first unit. The third information associates a logical address with a physical address in a second unit different from the first unit. The memory controller caches the second information only in a first way. The memory controller caches the third information only in a second way different from the first way.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller executes access to the nonvolatile memory based on a command from a host device. The controller includes a processor, a data memory and a monitoring circuit. The monitoring circuit monitors writing to the data memory by a certain processing circuit in the controller and transmits a first notification to the processor when receiving the writing.

Abstract: A memory controller according to the embodiment includes a front-end unit that issues an invalidation command in response to a command from outside of the memory controller, the command including a logical address, an address translation unit that stores a correspondence relationship between the logical and a physical address, an invalidation command processing unit that, when the invalidation command is received, registers the logical address associated with the invalidation command as an invalidation registration region in an invalidation registration unit and issues a notification to the front-end unit, and an internal processing unit that dissolves a correspondence relationship between the logical address registered in the invalidation registration unit and the physical address in the address translation unit in a predetermined order by referencing the logical address registered in the invalidation registration unit.

Abstract: According to one embodiment, a memory system includes a first memory including a message queue having first to nth addresses (n?2, n is natural number), a first pointer showing one of the first to nth addresses, and a second pointer showing one of the first to nth addresses, a monitor unit which detects whether the first and second pointers show the first address, and a processing unit which changes an address shown by the first pointer from the first address to an ith address (n?i?2, i is natural number) when the first and second pointers show the first address. An address shown by the second pointer is incremented from the first address to a (j+1)th address (j?1, j is natural number) when first to jth messages are queued in the first to jth addresses.

Abstract: According to one embodiment, a memory system includes a nonvolatile first memory, a second memory which has a buffer, and a memory controller. The memory controller manages a plurality of pieces of translation information. In a case where the plurality of pieces of translation information include a first plurality of pieces of translation information, the memory controller caches first translation information among the first plurality of pieces of translation information and does not cache second translation information among the first plurality of pieces of translation information. The first plurality of pieces of translation information linearly correlates a plurality of continuous physical addresses with a plurality of continuous logical addresses.

Abstract: According to one embodiment, a memory system includes a nonvolatile first memory, a second memory which has a buffer, and a memory controller. The memory controller manages a plurality of pieces of translation information. In a case where the plurality of pieces of translation information include a first plurality of pieces of translation information, the memory controller caches first translation information among the first plurality of pieces of translation information and does not cache second translation information among the first plurality of pieces of translation information. The first plurality of pieces of translation information linearly correlates a plurality of continuous physical addresses with a plurality of continuous logical addresses.