Abstract: According to one embodiment, a memory system includes a first memory including a message queue having first to nth addresses (n?2, n is natural number), a first pointer showing one of the first to nth addresses, and a second pointer showing one of the first to nth addresses, a monitor unit which detects whether the first and second pointers show the first address, and a processing unit which changes an address shown by the first pointer from the first address to an ith address (n?i?2, i is natural number) when the first and second pointers show the first address. An address shown by the second pointer is incremented from the first address to a (j+1)th address (j?1, j is natural number) when first to jth messages are queued in the first to jth addresses.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller executes access to the nonvolatile memory based on a command from a host device. The controller includes a processor, a data memory and a monitoring circuit. The monitoring circuit monitors writing to the data memory by a certain processing circuit in the controller and transmits a first notification to the processor when receiving the writing.

Abstract: A memory controller according to the embodiment includes a front-end unit that issues an invalidation command in response to a command from outside of the memory controller, the command including a logical address, an address translation unit that stores a correspondence relationship between the logical and a physical address, an invalidation command processing unit that, when the invalidation command is received, registers the logical address associated with the invalidation command as an invalidation registration region in an invalidation registration unit and issues a notification to the front-end unit, and an internal processing unit that dissolves a correspondence relationship between the logical address registered in the invalidation registration unit and the physical address in the address translation unit in a predetermined order by referencing the logical address registered in the invalidation registration unit.

Abstract: According to one embodiment, a memory controller includes an encoding unit that generates a first code word, a duplication unit that duplicates the first code word, a memory interface that writes a code word group including the first code word and code words being duplicates of the first code word into a non-volatile memory, and reads the code words forming the code word group from the non-volatile memory, a determination unit that obtains a result of majority decision using the first code word and the plurality of code words, which are included in the code word group read from the non-volatile memory, and a decoding unit that decodes a code word being the result of the majority decision and corrects an error.

Abstract: A memory controller according to the embodiment includes a front-end unit that issues an invalidation command in response to a command from outside of the memory controller, the command including a logical address, an address translation unit that stores a correspondence relationship between the logical and a physical address, an invalidation command processing unit that, when the invalidation command is received, registers the logical address associated with the invalidation command as an invalidation registration region in an invalidation registration unit and issues a notification to the front-end unit, and an internal processing unit that dissolves a correspondence relationship between the logical address registered in the invalidation registration unit and the physical address in the address translation unit in a predetermined order by referencing the logical address registered in the invalidation registration unit.

Abstract: According to one embodiment, a memory system includes a non-volatile first storage unit, a second storage unit, a third storage unit, and a controller. The controller is configured to selectively execute, following transition to a first mode, either a procedure of writing data of the second storage unit in the third storage unit, or a procedure of writing data of the third storage unit in the first storage unit while reducing power feed to the first and third storage units.

Abstract: According to one embodiment, a data transfer control device complying with a communication protocol which executes an update of information from an attachment device in a predetermined area of a system memory, the device includes a receiving part receiving the information from the attachment device, a transferring part transferring the information in the predetermined area, the information from the transferring part overwritten in the predetermined area sequentially, and a determining part inhibiting a transfer of the information in the transferring part to omit the update of the information in the predetermined area.

Abstract: According to one embodiment, a storage device includes, when power is supplied to a storage unit, counting of an elapsed time is started. If a command is input from a host device, and the elapsed time from input of a previous command to input of a current command is calculated based on time information clocked by the host device and on a counter value counted until the corresponding command is input. Matching of the time information is determined based on a temporal relation between the adding result of adding the calculated elapsed time to the time information included in the previous command and the time information included in the current command. When the mismatching is determined, data in the storage unit is invalidated.

Abstract: According to one embodiment, a memory controller includes an encoding unit that generates a first code word, a duplication unit that duplicates the first code word, a memory interface that writes a code word group including the first code word and code words being duplicates of the first code word into a non-volatile memory, and reads the code words forming the code word group from the non-volatile memory, a determination unit that obtains a result of majority decision using the first code word and the plurality of code words, which are included in the code word group read from the non-volatile memory, and a decoding unit that decodes a code word being the result of the majority decision and corrects an error.

Abstract: A memory system in embodiments includes a nonvolatile semiconductor memory that stores user data, a forward lookup address translation table and a reverse lookup address translation table, and a controller. The controller is configured to determine that the user data stored in the nonvolatile semiconductor memory is valid or invalid based on these two tables. The controller may perform data organizing of selecting data determined valid and rewriting the data in a new block. The controller may perform write processing and rewriting processing to the new block alternately at a predetermined ratio. The controller may determine whether a predetermined condition is satisfied on a basis of addresses included in write requests and write data in the MLC mode when the condition is satisfied and write data in the SLC mode when the condition is not satisfied.

Abstract: According to one embodiment, a storage device includes, when power is supplied to a storage unit, counting of an elapsed time is started. If a command is input from a host device, and the elapsed time from input of a previous command to input of a current command is calculated based on time information clocked by the host device and on a counter value counted until the corresponding command is input. Matching of the time information is determined based on a temporal relation between the adding result of adding the calculated elapsed time to the time information included in the previous command and the time information included in the current command. When the mismatching is determined, data in the storage unit is invalidated.

Abstract: According to one embodiment, a controller registers first information to a first management table, and manage the first information, the first information being management information of data buffered in the buffer memory. When the data buffered in the buffer memory is flushed to the nonvolatile memory, the controller releases, from the first management table, the first information of the flushed data, and registers, to a second management table, and manages, the first information of the flushed data.

Abstract: According to one embodiment, a memory system includes a non-volatile first storage unit, a second storage unit, a third storage unit, and a controller. The controller is configured to selectively execute, following transition to a first mode, either a procedure of writing data of the second storage unit in the third storage unit, or a procedure of writing data of the third storage unit in the first storage unit while reducing power feed to the first and third storage units.

Abstract: According to one embodiment, a storage device that has a nonvolatile semiconductor memory includes an authentication information storage unit that previously stores first apparatus authentication information to authenticate an authorized host device and first user authentication information to authenticate an authorized user. The storage device executes apparatus authentication on the basis of second apparatus authentication information received from a newly connected host device and the first apparatus authentication information in the authentication information storage unit and executes an invalidation process of user data stored in the nonvolatile semiconductor memory, when the apparatus authentication is failed.

Abstract: According to one embodiment, a storage device includes, when power is supplied to a storage unit, counting of an elapsed time is started. If a command is input from a host device, and the elapsed time from input of a previous command to input of a current command is calculated based on time information clocked by the host device and on a counter value counted until the corresponding command is input. Matching of the time information is determined based on a temporal relation between the adding result of adding the calculated elapsed time to the time information included in the previous command and the time information included in the current command. When the mismatching is determined, data in the storage unit is invalidated.

Abstract: According to one embodiment, a storage device that has a nonvolatile semiconductor memory includes an authentication information storage unit that previously stores first apparatus authentication information to authenticate an authorized host device and first user authentication information to authenticate an authorized user. The storage device executes apparatus authentication on the basis of second apparatus authentication information received from a newly connected host device and the first apparatus authentication information in the authentication information storage unit and executes an invalidation process of user data stored in the nonvolatile semiconductor memory, when the apparatus authentication is failed.

Abstract: According to one embodiment, a semiconductor storage device includes a nonvolatile memory, memory controller storing control information, a switch between the nonvolatile memory/memory controller and a power supply terminal, a second memory, an interpreter interprets a command, a switch controller, and a third memory stores an address of the control information in the second memory. The memory controller instructs the switch controller to open the switch after writing the control information into the second memory and reads the control information from the second memory based on the address stored in the third memory when the memory controller is electrically connected to the first power supply terminal.

Abstract: According to one embodiment, a memory controller includes a mode selection part that selects one of a MLC-mode and a SLC-mode, after a write command is decoded by a command decode part, and a write part that executes a data writing to a storage memory by using one of the MLC-mode and the SLC-mode selected by the mode selection part. The mode selection part is configured to check whether a first data wrote from a host to a buffer memory is a time-continuous data that is wrote continuously during a predetermined period, execute the data writing of a second data from the buffer memory to the storage memory in the MLC-mode, when the first data is the time-continuous data, and execute the data writing of the second data from the buffer memory to the storage memory in the SLC-mode, when the first data is not the time-continuous data.

Abstract: According to one embodiment, a data transfer control device complying with a communication protocol which executes an update of information from an attachment device in a predetermined area of a system memory, the device includes a receiving part receiving the information from the attachment device, a transferring part transferring the information in the predetermined area, the information from the transferring part overwritten in the predetermined area sequentially, and a determining part inhibiting a transfer of the information in the transferring part to omit the update of the information in the predetermined area.

Abstract: A management information generating method wherein logical and physical block addresses (BAs) of continuous addresses are associated with each other in the BA translation table. When a logical block is constructed, a value is set for a maximum number of allowable defective physical blocks. A logical block having fewer defects than the set number is set usable, and a logical block having more defects than the set number is set unusable. System logical block construction is performed to preferentially select physical blocks from a plane list including a large number of usable blocks to equalize the number of usable blocks in each plane list. It is determined whether the number of free blocks is insufficient on the basis of a first management unit and whether the storage area for the indicated capacity can be reserved on the basis of the management unit different from the first unit.