Patents by Inventor Mitsutaka Sato

Mitsutaka Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7064645
    Abstract: The present invention realizes a miniaturized electronic device that is still capable of maintaining its high reliability even when miniaturized. To this end, the electronic device has an electronic circuit, comprising: a substrate with a circuit formation surface on which one part of the electronic circuit is formed; a polyimide layer that is formed on the circuit formation surface; and a spiral inductor constituting another part of the electronic circuit, which is formed into a pattern on the polyimide layer.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: June 20, 2006
    Assignee: Fujitsu Limited
    Inventors: Kazuhiko Kobayashi, Hideharu Sakoda, Hirohisa Matsuki, Osamu Igawa, Mitsutaka Sato, Koju Aoki, Hiroyuki Sakima
  • Publication number: 20060040532
    Abstract: A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.
    Type: Application
    Filed: December 23, 2004
    Publication date: February 23, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Kaname Ozawa, Mitsutaka Sato, Tetsuya Fujisawa, Yoshiyuki Yoneda, Ryuji Nomoto, Yoshitaka Aiba
  • Patent number: 6967399
    Abstract: A semiconductor device including a semiconductor element having an electrode pad, a mounting terminal for mounting a substrate, an adhesive layer provided on the semiconductor element, and a wiring electrically connecting the electrode pad to the mounting terminal. The wiring includes a metal foil and a metal film layer. The entire metal foil is in contact with the adhesive layer, and the metal film layer is in contact with the electrode pad.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: November 22, 2005
    Assignee: Fujitsu Limited
    Inventors: Yoshitaka Aiba, Mitsutaka Sato
  • Patent number: 6909181
    Abstract: There are provided a sealing insulating film that is formed on a substrate and melted at a first heating temperature to have a flowability, and external terminals that are formed on the substrate, and connected to other electronic device at a second heating temperature higher than the first heating temperature, and surrounded by the sealing insulating film.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: June 21, 2005
    Assignee: Fujitsu Limited
    Inventors: Yoshitaka Aiba, Hirohisa Matsuki, Mitsutaka Sato
  • Patent number: 6905951
    Abstract: A semiconductor device substrate has fine terminals with a small pitch and is able to be easily produced at a low cost without using a special process. A mounting terminal has a pyramidal shape and extending between a front surface and a back surface of a silicon substrate. An end of the mounting terminal protrudes from the back surface of the silicon substrate. A wiring layer is formed on the front surface of the silicon substrate. The wiring layer includes a conductive layer that is electrically connected to the mounting terminal.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: June 14, 2005
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Yoneda, Masaharu Minamizawa, Eiji Watanabe, Mitsutaka Sato
  • Publication number: 20050001329
    Abstract: A semiconductor device includes a first semiconductor chip (5) having a first terminal (7) on one surface, a second semiconductor chip (1a) which is larger than the first semiconductor chip (5) and on which the first semiconductor chip (5) is stacked and which has a second terminal (3) on one surface, an insulating layer (10) formed on a second semiconductor chip (1a) to cover the first semiconductor chip (5), a plurality of holes (10a) formed in the insulating layer (10) on at least a peripheral area of the first semiconductor chip (5), a via (11a) formed like a film on inner peripheral surfaces and bottom surfaces of the holes (10a) and connected electrically to the second terminal (3) of the second semiconductor chip (1a), a wiring pattern (11b) formed on an upper surface of the insulating layer (10), and an external terminal (14) formed on the wiring pattern (11b).
    Type: Application
    Filed: June 4, 2004
    Publication date: January 6, 2005
    Inventors: Hirohisa Matsuki, Yoshitaka Aiba, Mitsutaka Sato, Tadahiro Okamato
  • Patent number: 6836025
    Abstract: In a semiconductor device circuit formation surfaces of each of a plurality of semiconductor chips can be easily located at even level when the semiconductor chips are arranged side by side so that a process of forming rearrangement wiring is simplified. The semiconductor chips are mounted on a substrate via an adhesive layer in a two-dimensional arrangement. A resin layer is formed on the substrate and located around the semiconductor elements. The resin layer has the same thickness as a thickness of the semiconductor elements. An organic insulating layer is formed over a surface of the resin layer and circuit formation surfaces of the semiconductor elements. A rearrangement wiring layer is formed on the organic insulating layer and electrodes of the semiconductor chips. External connection terminals are electrically connected to the circuit formation surfaces of the semiconductor elements through wiring in the rearrangement wiring layer.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: December 28, 2004
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Fujisawa, Hirohisa Matsuki, Osamu Igawa, Yoshitaka Aiba, Masamitsu Ikumo, Mitsutaka Sato
  • Publication number: 20040224499
    Abstract: A semiconductor device substrate has fine terminals with a small pitch and is able to be easily produced at a low cost without using a special process. A mounting terminal has a pyramidal shape and extending between a front surface and a back surface of a silicon substrate. An end of the mounting terminal protrudes from the back surface of the silicon substrate. A wiring layer is formed on the front surface of the silicon substrate. The wiring layer includes a conductive layer that is electrically connected to the mounting terminal.
    Type: Application
    Filed: June 8, 2004
    Publication date: November 11, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiyuki Yoneda, Masaharu Minamizawa, Eiji Watanabe, Mitsutaka Sato
  • Publication number: 20040171741
    Abstract: Generation of air marks and flow marks is prevented when a vinyl chloride resin is molded into a sheet or the like. To a vinyl chloride resin is added a processing aid for a vinyl chloride resin comprising a copolymer composition containing, (A) 70 to 99 parts by weight of a copolymer obtained by polymerizing a monomer mixture comprising 50 to 99% by weight of methyl methacrylate, 1 to 50% by weight of an aromatic vinyl compound and 0 to 30% by weight of another monomer copolymerizable with these components, said copolymer having a specific viscosity at 30° C. of 0.3 to 1.8 when 0.
    Type: Application
    Filed: January 6, 2004
    Publication date: September 2, 2004
    Inventors: Mitsutaka Sato, Takenobu Sunagawa, Mamoru Kadokura
  • Patent number: 6784543
    Abstract: A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: August 31, 2004
    Assignee: Fujitsu Limited
    Inventors: Hirohisa Matsuki, Yutaka Makino, Masamitsu Ikumo, Mitsutaka Sato, Tetsuya Fujisawa, Yoshitaka Aiba
  • Patent number: 6781224
    Abstract: A semiconductor device substrate has fine terminals with a small pitch and is able to be easily produced at a low cost without using a special process. A mounting terminal has a pyramidal shape and extending between a front surface and a back surface of a silicon substrate. An end of the mounting terminal protrudes from the back surface of the silicon substrate. A wiring layer is formed on the front surface of the silicon substrate. The wiring layer includes a conductive layer that is electrically connected to the mounting terminal.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: August 24, 2004
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Yoneda, Masaharu Minamizawa, Eiji Watanabe, Mitsutaka Sato
  • Patent number: 6723762
    Abstract: There is provided a foamable poly(vinyl chloride) resin composition which can remarkably improve an expansion ratio. There is used a foamable poly(vinyl chloride) resin composition comprising 100 parts by weight of (A) a poly(vinyl chloride) resin, 0.5 to 30 parts by weight of (B) a processing aid, and 0.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: April 20, 2004
    Assignee: Kaneka Corporation
    Inventors: Takenobu Sunagawa, Noriko Sakashita, Mitsutaka Sato, Mamoru Kadokura
  • Patent number: 6696754
    Abstract: A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: February 24, 2004
    Assignee: Fujitsu Limited
    Inventors: Mitsutaka Sato, Tetsuya Fujisawa, Shigeyuki Maruyama, Junichi Kasai, Toshimi Kawahara, Toshio Hamano, Yoshihiro Kubota, Mitsunada Osawa, Yoshiyuki Yoneda, Kazuto Tsuji, Hirohisa Matsuki
  • Publication number: 20030227095
    Abstract: In a semiconductor device circuit formation surfaces of each of a plurality of semiconductor chips can be easily located at even level when the semiconductor chips are arranged side by side so that a process of forming rearrangement wiring is simplified. The semiconductor chips are mounted on a substrate via an adhesive layer in a two-dimensional arrangement. A resin layer is formed on the substrate and located around the semiconductor elements. The resin layer has the same thickness as a thickness of the semiconductor elements. An organic insulating layer is formed over a surface of the resin layer and circuit formation surfaces of the semiconductor elements. A rearrangement wiring layer is formed on the organic insulating layer and electrodes of the semiconductor chips. External connection terminals are electrically connected to the circuit formation surfaces of the semiconductor elements through wiring in the rearrangement wiring layer.
    Type: Application
    Filed: May 30, 2003
    Publication date: December 11, 2003
    Inventors: Tetsuya Fujisawa, Hirohisa Matsuki, Osamu Igawa, Yoshitaka Aiba, Masamitsu Ikumo, Mitsutaka Sato
  • Publication number: 20030207574
    Abstract: A method of manufacturing a semiconductor device is provided. The method comprises a wire-forming step of forming a wiring on a substrate having an electrode pad so as to connect the electrode pad to a mounting terminal. The wire-forming step includes the steps of: applying a metal foil to the substrate by providing an adhesive therebetween; patterning the metal foil into a predetermined pattern so as to form the wiring; and connecting the wiring to the electrode pad electrically.
    Type: Application
    Filed: May 23, 2003
    Publication date: November 6, 2003
    Applicant: Fujitsu Limited
    Inventors: Yoshitaka Aiba, Mitsutaka Sato
  • Patent number: 6635687
    Abstract: An expandable vinyl chloride resin composition which can provide foamed articles having a greatly enhanced expansion ratio without remarkably lowering the surface property and strength by the use of thermally decomposable blowing agents without the use of organic solvent blowing agents, and which comprises 100 parts by weight of a vinyl chloride resin, 0.5 to 30 parts by weight of, as a processing aid, a two stage (meth)acrylic ester polymer having a specific viscosity of at least 0.5 (0.1 % chloroform solution, 30° C.) prepared by polymerizing a monomer component containing as a main component a monomer selected from acrylic esters and methacrylic esters excepting methyl methacrylate in the presence of a latex of a methyl methacrylate polymer having a specific viscosity of at least 0.7, 0.3 to 25 parts by weight of a thermally decomposable inorganic blowing agent, 0.01 to 15 parts by weight of a thermally decomposable organic blowing agent and 0 to 20 parts by weight of a filler.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: October 21, 2003
    Assignee: Kaneka Corporation
    Inventors: Takenobu Sunagawa, Mitsutaka Sato, Mamoru Kadokura
  • Patent number: 6627479
    Abstract: A plurality of semiconductor chips are incorporated in a one-piece package so as to substantially increase a mounting area of a semiconductor device so that the semiconductor device can be provided with the projection electrodes having a structure which enable the semiconductor device to be mounted by a conventional surface mounting technique. A redistribution layer interconnects and integrally holds the plurality of semiconductor elements. A plurality of projection electrodes are provided on the redistribution layer for surface mounting. The plurality of semiconductor chips are rendered to be different kinds so that the plurality of different kinds of semiconductor chips together provide a complete function. The plurality of semiconductor chips may be rendered to be the same kind so as to reduce a mounting area of the semiconductor chips as a whole.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: September 30, 2003
    Assignee: Fujitsu, Limited
    Inventors: Yoshitaka Aiba, Mitsutaka Sato, Toshio Hamano
  • Publication number: 20030164544
    Abstract: A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.
    Type: Application
    Filed: August 8, 2002
    Publication date: September 4, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Mitsutaka Sato, Tetsuya Fujisawa, Shigeyuki Maruyama, Junichi Kasai, Toshimi Kawahara, Toshio Hamano, Yoshihiro Kubota, Mitsunada Osawa, Yoshiyuki Yoneda, Kazuto Tsuji, Hirohisa Matsuki
  • Publication number: 20030160325
    Abstract: A semiconductor device substrate has fine terminals with a small pitch and is able to be easily produced at a low cost without using a special process. A mounting terminal has a pyramidal shape and extending between a front surface and a back surface of a silicon substrate. An end of the mounting terminal protrudes from the back surface of the silicon substrate. A wiring layer is formed on the front surface of the silicon substrate. The wiring layer includes a conductive layer that is electrically connected to the mounting terminal.
    Type: Application
    Filed: October 2, 2002
    Publication date: August 28, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiyuki Yoneda, Masaharu Minamizawa, Eiji Watanabe, Mitsutaka Sato
  • Patent number: 6610757
    Abstract: An expandable vinyl chloride resin composition that the expansion ratio of a vinyl chloride resin can be greatly increased by the use of thermally decomposable inorganic blowing agents without the use of organic solvent blowing agents, and which comprises 100 parts by weight of a vinyl chloride resin, 0.5 to 30 parts by weight of, as a processing aid, a (meth)acrylic acid ester polymer having a specific viscosity of not less than 0.73 measured at 30° C. with respect to a solution of 0.1 g of the polymer dissolved in 100 ml of chloroform, and not less than 0.3 to less than 2 parts by weight of a thermally decomposable inorganic blowing agent such as sodium bicarbonate.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: August 26, 2003
    Assignee: Kaneka Corporation
    Inventors: Takenobu Sunagawa, Mitsutaka Sato, Noriko Sakashita, Mamoru Kadokura