Patents by Inventor Mitsutaka Sato

Mitsutaka Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6333564
    Abstract: A semiconductor device and a method of producing the same, the device including a semiconductor chip; balls which function as external connecting terminals; a substrate which electrically connects the semiconductor chip and the balls; a mold resin which seals at least a part of the semiconductor chip; and a connecting portion sealing resin which seals the connecting portion between the substrate and the semiconductor chip. The semiconductor device is mounted onto a printed circuit board via the balls. The thermal expansion coefficient of the mold resin is matched with the thermal expansion coefficient of the printed circuit board. A side surface holding portion for the holding the side surfaces of the semiconductor chip is formed in the mold resin to restrict thermal deformation of the semiconductor chip.
    Type: Grant
    Filed: June 21, 1999
    Date of Patent: December 25, 2001
    Assignee: Fujitsu Limited
    Inventors: Yoshitsugu Katoh, Mitsutaka Sato, Hiroshi Inoue, Seiichi Orimo, Akira Okada, Yoshihiro Kubota, Mitsuo Abe, Toshio Hamano, Yoshitaka Aiba, Tetsuya Fujisawa, Masaaki Seki, Noriaki Shiba
  • Publication number: 20010052653
    Abstract: A semiconductor device and a method of producing the semiconductor device are provided. This semiconductor device includes a semiconductor chip, a printed wiring board, a heat spreader, a sealing resin, and solder balls. The printed wiring board is provided with the solder balls on an outer portion and a wiring layer on an inner portion. Wires are bonded to the wiring layer, and an opening is formed in the center of the printed wiring board. The heat spreader is bonded to the printed wiring board, with the semiconductor chip being thermally connected to the stage portion of the heat spreader. The sealing resin is made up of a first sealing resin portion and a second sealing resin portion. The first and second sealing resin portions sandwich the heat spreader.
    Type: Application
    Filed: July 13, 2001
    Publication date: December 20, 2001
    Inventors: Mitsuo Abe, Yoshihiro Kubota, Yoshitsugu Katoh, Michio Hayakawa, Ryuji Nomoto, Mitsutaka Sato, Seiichi Orimo, Hiroshi Inoue, Toshio Hamano
  • Patent number: 6316838
    Abstract: A semiconductor device includes a substrate provided with a plurality of leads, a face-down semiconductor element provided on one surface of the substrate, a first stacked semiconductor element and a second stacked semiconductor element provided on another surface of the substrate and connected to the substrate by wires, and an extended wiring mechanism for connecting electrodes of the face-down semiconductor element and electrodes of the first and second semiconductor elements. The connected electrodes are equi-electrodes whose electrical characteristics are equal.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: November 13, 2001
    Assignee: Fujitsu Limited
    Inventors: Kaname Ozawa, Hayato Okuda, Tetsuya Hiraoka, Mitsutaka Sato, Yuji Akashi, Akira Okada, Masahiko Harayama
  • Patent number: 6288444
    Abstract: A semiconductor device and a method of producing the semiconductor device are provided. This semiconductor device includes a semiconductor chip, a printed wiring board, a heat spreader, a sealing resin, and solder balls. The printed wiring board is provided with the solder balls on an outer portion and a wiring layer on an inner portion. Wires are bonded to the wiring layer, and an opening is formed in the center of the printed wiring board. The heat spreader is bonded to the printed wiring board, with the semiconductor chip being thermally connected to the stage portion of the heat spreader. The sealing resin is made up of a first sealing resin portion and a second sealing resin portion. The first and second sealing resin portions sandwich the heat spreader.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: September 11, 2001
    Assignee: Fujitsu Limited
    Inventors: Mitsuo Abe, Yoshihiro Kubota, Yoshitsugu Katoh, Michio Hayakawa, Ryuji Nomoto, Mitsutaka Sato, Seiichi Orimo, Hiroshi Inoue, Toshio Hamano
  • Patent number: 6165819
    Abstract: A method of producing a semiconductor device includes a device body producing step, electrically coupling leads and a semiconductor chip, and producing a device body by encapsulating the semiconductor chip by a resin package so that portions of the leads are exposed from the resin package, a honing step, carrying out a honing process using a polishing solution at least with respect to a resin flash adhered on the portions of the leads exposed from the resin package, an etching step, removing an unwanted stacked layer structure formed on the leads by carrying out an etching process after the honing step, and a plating step, carrying out a plating process with respect to the leads after the etching step to form a plated layer made of a soft bonding material. The honing step removes a portion of the unwanted stacked layer structure in addition to the resin flash.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: December 26, 2000
    Assignee: Fujitsu Limited
    Inventors: Masaaki Seki, Katsuhiro Hayashida, Mitsutaka Sato, Toshio Hamano
  • Patent number: 6094356
    Abstract: A semiconductor device including a semiconductor chip, connection parts arranged along one end of the semiconductor chip, and external connection terminals connected to the connection parts.
    Type: Grant
    Filed: January 16, 1998
    Date of Patent: July 25, 2000
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Fujisawa, Mitsutaka Sato, Kazuhiko Mitobe, Katsuhiro Hayashida, Masaaki Seki, Seiichi Orimo, Toshio Hamano
  • Patent number: 6084309
    Abstract: A semiconductor device includes a semiconductor chip, a package encapsulating the semiconductor chip, a plurality of leads each having one end electrically connected to the semiconductor chip and another end exposed at a wall surface of the package to form an external terminal, where each of the leads excluding the external terminal is encapsulated within the package, and a lead projection provided on the external terminal of the lead. This lead projection projects from the wall surface of the package, so that a thickness of a soft bonding material provided on the external terminal can be increased to provide an improved bonding and connection when mounting the semiconductor device on a circuit substrate.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: July 4, 2000
    Assignee: Fujitsu Limited
    Inventors: Toyoshige Kawashima, Mitsutaka Sato, Tetsuya Fujisawa
  • Patent number: 6060768
    Abstract: A semiconductor device includes a semiconductor chip in which electrode pads are formed with a first pitch, leads electrically connected with the electrode pads through lines, and sealing plastic sealing the semiconductor chip. In the semiconductor device, projections used for external connection ports are formed in the leads with a second pitch. The sealing plastic seals the lines connecting the electrode pads and the leads, but the projections are exposed from the sealing plastic.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: May 9, 2000
    Assignee: Fujitsu Limited
    Inventors: Katsuhiro Hayashida, Mitsutaka Sato, Tadashi Uno, Tetsuya Fujisawa, Masaki Waki
  • Patent number: 5984699
    Abstract: A lead frame is formed by subjecting a frame base to a forming process, a semiconductor chip is fixed on leads formed in the lead frame and wires are provided in the semiconductor chip, and then a package which accommodates the semiconductor chip is formed; a non-conductive adhesive being provided, before the forming process, on a position on the frame base in which the leads are formed, and unnecessary portions of the frame base and the non-conductive adhesive being removed in the forming process so that the leads having a predetermined configuration and provided with the non-conductive adhesive are formed.
    Type: Grant
    Filed: January 29, 1997
    Date of Patent: November 16, 1999
    Assignee: Fujitsu Limited
    Inventors: Masaki Waki, Katsuhiro Hayashida, Mitsutaka Sato, Tadashi Uno, Kazuhiko Mitobe, Tetsuya Fujisawa
  • Patent number: 5842628
    Abstract: A wire bonding method includes a first bonding process for forming a first ball-shaped part in a wire and bonding the first ball-shaped part to a first connected member; a ball-shaped part forming process for guiding the wire away from a position where the wire is bonded to an inner lead so as to form a predetermined loop, and forming a second ball-shaped part in a predetermined position in the wire; and a second bonding process for bonding the second ball-shaped part to a semiconductor element pad that serves as a second connected member.
    Type: Grant
    Filed: April 8, 1996
    Date of Patent: December 1, 1998
    Assignee: Fujitsu Limited
    Inventors: Ryuji Nomoto, Kazuto Tsuji, Mitsutaka Sato, Junichi Kasai
  • Patent number: 5821613
    Abstract: A method of manufacturing a semiconductor device which includes a semiconductor chip and a plastic package of a thermosetting polymer encapsulating the semiconductor chip through a molding process. The thermosetting polymer of the plastic package fully or partially covers a bottom surface of the semiconductor chip. An ultraviolet cleaning process is performed for cleaning the bottom surface of the semiconductor chip prior to the molding process.
    Type: Grant
    Filed: August 28, 1997
    Date of Patent: October 13, 1998
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Akira Takashima, Mitsutaka Sato, Shinichirou Taniguchi
  • Patent number: 5801439
    Abstract: A semiconductor device includes a semiconductor element, a package sealing the semiconductor element, and leads for passing signals between the semiconductor element and an external device. Each of the leads has an inner-lead part sealed within the package and connected with the semiconductor element, and an outer-lead part which extends outward from the package toward a top of the package, and is to be connected to the external device. The outer-lead part includes a first-port part at a lower side of the package, and a second-port part at an upper side of the package.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: September 1, 1998
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Fujisawa, Mitsutaka Sato, Junichi Kasai, Masataka Mizukoshi, Kosuke Otokita, Hiroshi Yoshimura, Katsuhiro Hayashida, Akira Takashima, Masahiko Ishiguri, Michio Sono
  • Patent number: 5786985
    Abstract: A semiconductor device is adapted to be mounted on a circuit substrate in an approximate vertical position. The semiconductor device includes a semiconductor chip, a stage having a first surface and a second surface opposite to the first surface, where the semiconductor chip is mounted on the first surface, a resin package encapsulating the semiconductor chip, where the resin package has upper and lower surfaces and side surfaces, a plurality of leads respectively having one end electrically connected to the semiconductor chip and another end extending downwardly from the lower surface of the resin package, and an upper extension, provided on the stage, extending upwardly from the upper surface of the resin package.
    Type: Grant
    Filed: November 15, 1996
    Date of Patent: July 28, 1998
    Assignee: Fujitsu Limited
    Inventors: Norio Taniguchi, Junichi Kasai, Kazuto Tsuji, Michio Sono, Masanori Yoshimoto, Katsuhiro Hayashida, Mitsutaka Sato, Hiroshi Yoshimura, Tadashi Uno, Kosuke Otokita, Tetsuya Fujisawa
  • Patent number: 5773313
    Abstract: A semiconductor device includes a semiconductor chip (11) having a top surface and a bottom surface, a plurality of leads (14) arranged under the bottom surface of the semiconductor chip (11), where the leads (14) have first ends (14a) electrically coupled to the semiconductor chip (11) and second ends which form external terminals (16) and each of the external terminals have a bottom surface, and a package (17, 31) encapsulating the semiconductor chip (11) and the leads (14) so that the bottom surface of each of the external terminals (16) is exposed at a bottom surface (17a, 31a) of the package (17, 31) and remaining portions of the leads (14) are embedded within the package (17, 31), where the package (17, 31) has a size which is approximately the same as that of the semiconductor chip (11) in a plan view viewed from above the top surface of the semiconductor chip (11).
    Type: Grant
    Filed: October 24, 1995
    Date of Patent: June 30, 1998
    Assignee: Fujitsu Limited
    Inventors: Mitsutaka Sato, Junichi Kasai
  • Patent number: 5760471
    Abstract: A semiconductor device including a semiconductor element, and leads connected with the semiconductor element. Each of the leads includes an outer lead part for being connected externally. The semiconductor device further includes a plastic package sealing the semiconductor element and the leads. In the semiconductor device, the outer lead part is exposed to the outside of a side face of the plastic package, and the plastic package is mounted on any base in a standing form by the side face contacting the base.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: June 2, 1998
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Fujisawa, Mitsutaka Sato, Junichi Kasai, Masataka Mizukoshi, Kousuke Otokita, Hiroshi Yoshimura, Katsuhiro Hayashida, Akira Takashima, Masahiko Ishiguri, Michio Sono
  • Patent number: 5728601
    Abstract: A process for manufacturing semiconductor package of a single in-line type including a semiconductor chip, a package body for accommodating the semiconductor chip and a plurality of leads held by the package body to extend substantially perpendicularly to a bottom edge surface of the package body. The package body carries a cutout part at a predetermined position of a side edge that surrounds the package body such that the cutout part is adapted for engagement with a support leg for supporting the package body substantially upright on a substrate.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: March 17, 1998
    Assignee: Fujitsu Limited
    Inventors: Mitsutaka Sato, Masanori Yoshimoto
  • Patent number: 5637915
    Abstract: A semiconductor device includes a semiconductor chip having top and bottom surfaces, upper leads electrically coupled to the semiconductor chip, where a first gap is formed between the upper leads and the top surface of the semiconductor chip, lower leads electrically coupled to the semiconductor chip, where a second gap is formed between the lower leads and the bottom surface of the semiconductor chip, and an encapsulating resin which encapsulates the semiconductor chip so as to maintain the first and second gaps.
    Type: Grant
    Filed: August 13, 1996
    Date of Patent: June 10, 1997
    Assignees: Fujitsu Ltd., Kyushu Fujitsu Electronics Ltd
    Inventors: Mitsutaka Sato, Junichi Kasai, Masanori Yoshimoto, Kouichi Takeshita
  • Patent number: 5519251
    Abstract: A semiconductor device includes a semiconductor chip (11) having a top surface and a bottom surface, a plurality of leads (14) arranged under the bottom surface of the semiconductor chip (11), where the leads (14) have first ends (14a) electrically coupled to the semiconductor chip (11) and second ends which form external terminals (16) and each of the external terminals have a bottom surface, and a package (17, 31) encapsulating the semiconductor chip (11) and the leads (14) so that the bottom surface of each of the external terminals (16) is exposed at a bottom surface (17a, 31a) of the package (17, 31) and remaining portions of the leads (14) are embedded within the package (17, 31), where the package (17, 31) has a size which is approximately the same as that of the semiconductor chip (11) in a plan view viewed from above the top surface of the semiconductor chip (11).
    Type: Grant
    Filed: October 15, 1993
    Date of Patent: May 21, 1996
    Assignee: Fujitsu Limited
    Inventors: Mitsutaka Sato, Junichi Kasai
  • Patent number: 5508565
    Abstract: A semiconductor device includes a first chip having a circuit arrangement, and a plurality of first terminals formed on a main surface of the first chip and substantially arranged into a line. The semiconductor device also includes a second chip having a circuit arrangement identical to that of the first chip, and a plurality of second terminals formed on a main surface of the second chip and substantially arranged into a line. The first and second chips are arranged in a predetermined direction perpendicular to the main surfaces of the first and second chips. The semiconductor device also includes a plurality of connecting members connected to the first terminals and the second terminals and provided for external connections.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: April 16, 1996
    Assignee: Fujitsu Limited
    Inventors: Atsushi Hatakeyama, Fumio Baba, Junichi Kasai, Mitsutaka Sato
  • Patent number: 5446317
    Abstract: A semiconductor package of a single in-line type including a semiconductor chip, a package body for accommodating the semiconductor chip and a plurality of leads held by the package body to extend substantially perpendicularly to a bottom edge surface of the package body. The package body carries a cutout part at a predetermined position of a side edge that surrounds the package body such that the cutout part is adapted for engagement with a support leg for supporting the package body substantially upright on a substrate.
    Type: Grant
    Filed: March 5, 1993
    Date of Patent: August 29, 1995
    Assignee: Fujitsu Limited
    Inventors: Mitsutaka Sato, Masanori Yoshimoto