Patents by Inventor Mitsuyoshi Mori
Mitsuyoshi Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8698064Abstract: A solid-state imaging device according to the present invention includes pixels which are arranged two-dimensionally and each of which includes: a light absorbing layer that converts light into signal charges; a signal read circuit to read out the signal charges, the signal read circuit being formed on a side opposite to a light incident plane side of the light absorbing layer; a metal layer that is formed on the light incident plane side of the light absorbing layer, the metal layer having an aperture to transmit, into the light absorbing layer, light of a wavelength range depending on a shape of the aperture, a driving circuit that applies a voltage to the metal layer to generate, in the light absorbing layer, a potential gradient to collect the signal charges.Type: GrantFiled: November 20, 2012Date of Patent: April 15, 2014Assignee: Panasonic CorporationInventors: Yusuke Otake, Yutaka Hirose, Mitsuyoshi Mori, Toru Okino, Yoshihisa Kato
-
Patent number: 8680640Abstract: A solid-state imaging device includes semiconductor substrate; a plurality of photoelectric conversion sections of n-type that are formed at an upper part of semiconductor substrate and arranged in a matrix; output circuit that is formed on a charge detection surface that is one surface of semiconductor substrate and detects charges stored in photoelectric conversion sections; a plurality of isolating diffusion layers of a p-type that are formed under output circuit and include high concentration p-type layers adjacent to respective photoelectric conversion sections; and color filters formed on a light incident surface that is the other surface opposing the one surface of semiconductor substrate and transmit light with different wavelengths. Shapes of respective photoelectric conversion sections correspond to color filters and differ depending on the high concentration p-type layer configuring isolating diffusion layer.Type: GrantFiled: May 3, 2012Date of Patent: March 25, 2014Assignee: Panasonic CorporationInventors: Mitsuyoshi Mori, Toru Okino, Yutaka Hirose, Yoshihisa Kato
-
Publication number: 20140054737Abstract: A solid-state imaging device includes: a substrate; an insulator layer formed on the substrate; a semiconductor layer formed on the insulator layer; and a silicon layer formed on the semiconductor layer. The silicon layer includes a plurality of pixels each including a photoelectric converter configured to convert light into signal charge, and a circuit configured to read the signal charge, and a refractive index of the insulator layer is lower than a refractive index of the semiconductor layer.Type: ApplicationFiled: October 30, 2013Publication date: February 27, 2014Applicant: PANASONIC CORPORATIONInventors: Toru OKINO, Mitsuyoshi MORI, Yutaka HIROSE, Yoshihisa KATO, Tsuyoshi TANAKA
-
Publication number: 20130314574Abstract: A solid-state imaging device includes: pixels arrayed two-dimensionally; pixel common circuits arrayed in a matrix, each shared by adjacent pixels of a certain number among the pixels; column common circuits, each provided for one of columns of the pixel common circuits, and shared by pixel common circuits belonging to a same column; column signal lines each provided for one of the columns of the pixel common circuits; and reset signal lines each provided for one of the columns of the pixel common circuits, in which an electric signal from each of the pixels is detected by a corresponding one of the pixel common circuits and read by a corresponding one of the column common circuits, and the electric signal detected by the corresponding one of the pixel common circuits is reset by a feedback path including one column signal line, one column common circuit, and one reset signal lines.Type: ApplicationFiled: August 1, 2013Publication date: November 28, 2013Applicant: Panasonic CorporationInventors: Motonori ISHII, Shigetaka KASUGA, Mitsuyoshi MORI
-
Patent number: 8592874Abstract: In each of pixels 10 arranged in an array pattern, an insulating isolation part 22 electrically isolates adjacent photoelectric conversion elements 11, and the photoelectric conversion element 11 and an amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. A low concentration first isolation diffusion layer 23 is formed below the insulating isolation part 22 constituting the first region A, and a high concentration second isolation diffusion layer 24 and a low concentration first isolation diffusion layer 23 are formed below the insulating isolation part 22 constituting the second region B. A source/drain region of the amplifier transistor 14 in the second region B is formed in a well region 25 formed simultaneously with the second isolation diffusion layer 24.Type: GrantFiled: August 4, 2011Date of Patent: November 26, 2013Assignee: Panasonic CorporationInventors: Mitsuyoshi Mori, Toru Okino, Yusuke Otake, Hitomi Fujiwara
-
Patent number: 8471351Abstract: Each of pixels 10 arranged in an array pattern includes a photoelectric conversion element 11, a transfer transistor 13 for transferring charges to a floating diffusion layer 12, and an amplifier transistor 14 for outputting the transferred charges to an output line. An insulating isolation part 22 isolates the adjacent photoelectric conversion elements 11, and isolates the photoelectric conversion element 11 and the amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. First and second isolation diffusion layers 23 and 24 are formed below the insulating isolation part 22, and the second isolation diffusion layer 24 is wider than the first isolation diffusion layer 23 in the first region A.Type: GrantFiled: August 4, 2011Date of Patent: June 25, 2013Assignee: Panasonic CorporationInventors: Mitsuyoshi Mori, Toru Okino, Yusuke Otake, Hitomi Fujiwara
-
Patent number: 8378401Abstract: A solid state imaging apparatus includes: a plurality of photoelectric conversion cells each including a plurality of photoelectric sections arranged in an array of at least two rows and two columns; a plurality of floating diffusion sections each being connected to each of ones of the photoelectric sections which are included in the same row of each said photoelectric conversion cell via each of a plurality of transfer transistors, and being shared by said ones of the photoelectric sections; a plurality of read-out lines each being selectively connected to at least two of the transfer transistors; and a plurality of pixel amplifier transistors each detecting and outputting the potential of each said the floating diffusion section. Charges of the photoelectric conversion sections each being connected to one of the read-out lines and being read out by the transfer transistors are read out by different floating diffusion sections.Type: GrantFiled: December 22, 2011Date of Patent: February 19, 2013Assignee: Panasonic CorporationInventors: Mitsuyoshi Mori, Takumi Yamaguchi, Takahiko Murata
-
Patent number: 8354693Abstract: A solid state imaging device includes a pixel having a photoelectric conversion element formed on a semiconductor substrate. The photoelectric conversion element includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer and forming a junction therebetween; a third semiconductor layer formed on the second semiconductor layer and having a smaller band gap energy than the second semiconductor layer, the third semiconductor layer being made of a single-crystal semiconductor and containing an impurity; and a fourth semiconductor layer of the first conductivity type covering a side surface and an upper surface of the third semiconductor layer. Provision of the fourth semiconductor layer can reduce a current flowing in dark conditions.Type: GrantFiled: February 21, 2008Date of Patent: January 15, 2013Assignee: Panasonic CorporationInventors: Mitsuyoshi Mori, Toru Okino, Daisuke Ueda, Toshinobu Matsuno
-
Publication number: 20120217494Abstract: Solid-state imaging device of the present invention is a backside-illumination-type solid-state imaging device including wiring layer formed on first surface side of semiconductor substrate; and light receiving section that photoelectrically converts light incident from second surface side that is opposite from first surface side, wherein spontaneous polarization film formed of a material having spontaneous polarization is formed on a light receiving surface of light receiving section. Accordingly, a hole accumulation layer can be formed on the light receiving surface of light receiving section, and a dark current can be suppressed.Type: ApplicationFiled: May 3, 2012Publication date: August 30, 2012Applicant: PANASONIC CORPORATIONInventors: TORU OKINO, YOSHIHISA KATO, YUTAKA HIROSE, MITSUYOSHI MORI
-
Publication number: 20120211851Abstract: A solid-state imaging device includes semiconductor substrate; a plurality of photoelectric conversion sections of n-type that are formed at an upper part of semiconductor substrate and arranged in a matrix; output circuit that is formed on a charge detection surface that is one surface of semiconductor substrate and detects charges stored in photoelectric conversion sections; a plurality of isolating diffusion layers of a p-type that are formed under output circuit and include high concentration p-type layers adjacent to respective photoelectric conversion sections; and color filters formed on a light incident surface that is the other surface opposing the one surface of semiconductor substrate and transmit light with different wavelengths. Shapes of respective photoelectric conversion sections correspond to color filters and differ depending on the high concentration p-type layer configuring isolating diffusion layer.Type: ApplicationFiled: May 3, 2012Publication date: August 23, 2012Applicant: PANASONIC CORPORATIONInventors: MITSUYOSHI MORI, TORU OKINO, YUTAKA HIROSE, YOSHIHISA KATO
-
Patent number: 8243176Abstract: A solid-state image sensor includes: a semiconductor substrate 22; a plurality of pixels 23 arranged on the semiconductor substrate 22 and respectively including photoelectric conversion regions 24; and an isolation region 25 electrically isolating the pixels 23 from one another. The first pixel 31 includes a first photoelectric conversion region 32 and a first color filter 41 having a peak of its optical transmission in a first wavelength range. The second pixel 34 adjacent to the first pixel 31 includes a second photoelectric conversion region 35 and a second color filter 42 having peaks in its optical transmission in the first wavelength range and a second wavelength range including shorter wavelengths than the first wavelength range. A portion 33 of a deep portion of the first photoelectric conversion region 32 extends across the isolation region 25 to reach a portion under the second photoelectric conversion region 35.Type: GrantFiled: June 2, 2009Date of Patent: August 14, 2012Assignee: Panasonic CorporationInventors: Yusuke Otake, Mitsuyoshi Mori, Shinzou Kouyama, Toru Okino
-
Publication number: 20120098040Abstract: A solid state imaging apparatus includes: a plurality of photoelectric conversion cells each including a plurality of photoelectric sections arranged in an array of at least two rows and two columns; a plurality of floating diffusion sections each being connected to each of ones of the photoelectric sections which are included in the same row of each said photoelectric conversion cell via each of a plurality of transfer transistors, and being shared by said ones of the photoelectric sections; a plurality of read-out lines each being selectively connected to at least two of the transfer transistors; and a plurality of pixel amplifier transistors each detecting and outputting the potential of each said the floating diffusion section. Charges of the photoelectric conversion sections each being connected to one of the read-out lines and being read out by the transfer transistors are read out by different floating diffusion sections.Type: ApplicationFiled: December 22, 2011Publication date: April 26, 2012Applicant: Panasonic CorporationInventors: Mitsuyoshi MORI, Takumi YAMAGUCHI, Takahiko MURATA
-
Patent number: 8115241Abstract: A semiconductor device of the present invention includes a substrate; an imaging region which is formed at part of the substrate and in which photoelectric conversion cells including photoelectric conversion sections are arranged in the form of an array; a control-circuit region which is formed at part of the substrate and in which the imaging region is controlled and a signal from the imaging region is outputted; and a copper-containing interconnect layer formed above the substrate and made of a material containing copper. Furthermore, a first anti-diffusion layer and a second anti-diffusion layer are formed, as anti-diffusion layers for preventing the copper from diffusing into each photoelectric conversion section, on the photoelectric conversion section and the copper-containing interconnect layer, respectively.Type: GrantFiled: September 18, 2008Date of Patent: February 14, 2012Assignee: Panasonic CorporationInventors: Mitsuyoshi Mori, Mikiya Uchida, Kazuo Fujiwara, Takumi Yamaguchi
-
Patent number: 8106431Abstract: A solid state imaging apparatus includes: a plurality of photoelectric conversion cells each including a plurality of photoelectric sections arranged in an array of at least two rows and two columns; a plurality of floating diffusion sections each being connected to each of ones of the photoelectric sections which are included in the same row of each said photoelectric conversion cell via each of a plurality of transfer transistors, and being shared by said ones of the photoelectric sections; a plurality of read-out lines each being selectively connected to at least two of the transfer transistors; and a plurality of pixel amplifier transistors each detecting and outputting the potential of each said the floating diffusion section. Charges of the photoelectric conversion sections each being connected to one of the read-out lines and being read out by the transfer transistors are read out by different floating diffusion sections.Type: GrantFiled: July 23, 2008Date of Patent: January 31, 2012Assignee: Panasonic CorporationInventors: Mitsuyoshi Mori, Takumi Yamaguchi, Takahiko Murata
-
Patent number: 8084796Abstract: A solid state imaging apparatus includes: a plurality of photoelectric conversion cells each including a plurality of photoelectric sections arranged in an array of at least two rows and two columns; a plurality of floating diffusion sections each being connected to each of ones of the photoelectric sections which are included in the same row of each said photoelectric conversion cell via each of a plurality of transfer transistors, and being shared by said ones of the photoelectric sections; a plurality of read-out lines each being selectively connected to at least two of the transfer transistors; and a plurality of pixel amplifier transistors each detecting and outputting the potential of each said the floating diffusion section. Charges of the photoelectric conversion sections each being connected to one of the read-out lines and being read out by the transfer transistors are read out by different floating diffusion sections.Type: GrantFiled: September 2, 2008Date of Patent: December 27, 2011Assignee: Panasonic CorporationInventors: Mitsuyoshi Mori, Takumi Yamaguchi, Takahiko Murata
-
Publication number: 20110291162Abstract: Each of pixels 10 arranged in an array pattern includes a photoelectric conversion element 11, a transfer transistor 13 for transferring charges to a floating diffusion layer 12, and an amplifier transistor 14 for outputting the transferred charges to an output line. An insulating isolation part 22 isolates the adjacent photoelectric conversion elements 11, and isolates the photoelectric conversion element 11 and the amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. First and second isolation diffusion layers 23 and 24 are formed below the insulating isolation part 22, and the second isolation diffusion layer 24 is wider than the first isolation diffusion layer 23 in the first region A.Type: ApplicationFiled: August 4, 2011Publication date: December 1, 2011Applicant: PANASONIC CORPORATIONInventors: Mitsuyoshi MORI, Toru Okino, Yusuke Otake, Kazuo Fujiwara, Hitomi Fujiwara
-
Publication number: 20110284929Abstract: In each of pixels 10 arranged in an array pattern, an insulating isolation part 22 electrically isolates adjacent photoelectric conversion elements 11, and the photoelectric conversion element 11 and an amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. A low concentration first isolation diffusion layer 23 is formed below the insulating isolation part 22 constituting the first region A, and a high concentration second isolation diffusion layer 24 and a low concentration first isolation diffusion layer 23 are formed below the insulating isolation part 22 constituting the second region B. A source/drain region of the amplifier transistor 14 in the second region B is formed in a well region 25 formed simultaneously with the second isolation diffusion layer 24.Type: ApplicationFiled: August 4, 2011Publication date: November 24, 2011Applicant: PANASONIC CORPORATIONInventors: Mitsuyoshi MORI, Kazuo Fujiwara, Toru Okino, Yusuke Otake, Hitomi Fujiwara
-
Patent number: 8035178Abstract: A plurality of pixel portions (12) are formed on a silicon substrate (11). A photoelectric converter portion (10) constituting each of the pixel portions (12) is electrically isolated by an element isolation portion (13) comprising an insulating film formed on the silicon substrate (11). The photoelectric converter portion (10) partitioned by the element isolation portion (13) is so formed that a crystal orientation of the sides in contact with the element isolation portion (13) corresponds to a <00-1> direction. This makes it possible to reduce dark current caused by stress in the vicinity of the interface of the element isolation portion (13) and maintain high sensitivity even if the pixel portions (12) are made smaller in size.Type: GrantFiled: June 24, 2008Date of Patent: October 11, 2011Assignee: Panasonic CorporationInventors: Mitsuyoshi Mori, Yasuhiro Shimada, Takuma Katayama, Kenji Taniguchi, Masayuki Furuhashi
-
Publication number: 20110121162Abstract: A solid-state imaging device that is configurable into a small size appropriate for expanding dynamic range includes: a photodiode which is a photoelectric conversion unit that generates charge by incident light; a MOS transistor which is connected to the photodiode and transfers the charge; a floating diffusion region which is a first accumulation unit which accumulates the charge via the MOS transistor; a MOS transistor which is a second transfer unit connected to the floating diffusion region and connected in series to the MOS transistor; and a MOS transistor which is an output unit which outputs, via the MOS transistor, a signal voltage in accordance with an amount of the charge.Type: ApplicationFiled: July 23, 2009Publication date: May 26, 2011Applicant: PANASONIC CORPORATIONInventors: Takahiko Murata, Takayoshi Yamada, Yoshihisa Kato, Shigetaka Kasuga, Mitsuyoshi Mori
-
Publication number: 20100327332Abstract: A solid state imaging device having a pixel area in which a plurality of light receiving elements are arranged, and a peripheral circuit area adjacent to the pixel area includes: a semiconductor substrate 102 of a first conductivity type or a second conductivity type; a first semiconductor layer 103 of the first conductivity type provided on the semiconductor substrate 102, where the first semiconductor layer 103 is lower in impurity concentration than the semiconductor substrate 102; first impurity regions 104 of the second conductivity type provided in upper portions of the first semiconductor layer 103 in the pixel area; second impurity regions 105 of the first conductivity type provided between the plurality of the first impurity regions 104 adjacent to each other in the pixel area and in the peripheral circuit area; and third impurity regions 106 of the first conductivity type expanded from a position directly under the second impurity regions 105 toward the semiconductor substrate 102 in the pixel area.Type: ApplicationFiled: June 29, 2009Publication date: December 30, 2010Inventors: Toru Okino, Mitsuyoshi Mori, Kazuo Jujiwara