Patents by Inventor Mizue Ishikawa

Mizue Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130248941
    Abstract: A spin transistor according to an embodiment includes: a semiconductor layer including a p+-region and an n+-region located at a distance from each other, and an i-region located between the p+-region and the n+-region; a first electrode located on the p+-region, the first electrode including a first ferromagnetic layer; a second electrode located on the n+-region, the second electrode including a second ferromagnetic layer; and a gate located on at least the i-region.
    Type: Application
    Filed: January 25, 2013
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomoaki Inokuchi, Mizue Ishikawa, Hideyuki Sugiyama, Yoshiaki Saito
  • Patent number: 8487359
    Abstract: It is made possible to provide a spin MOSFET that can minimize the increase in production costs and can perform both spin injection writing and reading. A spin MOSFET includes: a substrate that has a semiconductor region of a first conductivity type; first and second ferromagnetic stacked films that are formed at a distance from each other on the semiconductor region, and each have the same stacked structure comprising a first ferromagnetic layer, a nonmagnetic layer, and a second ferromagnetic layer stacked in this order, the second ferromagnetic stacked film having a film-plane area different from that of the first ferromagnetic stacked film; a gate insulating film that is formed on a portion of the semiconductor region, the portion being located between the first ferromagnetic stacked film and the second ferromagnetic stacked film; and a gate that is formed on the gate insulating film.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: July 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi, Mizue Ishikawa, Takao Marukame
  • Publication number: 20130075843
    Abstract: A spin transistor according to an embodiment includes: a first magnetic layer formed above a substrate and serving as one of a source and a drain; an insulating film having a lower face facing to an upper face of the first magnetic layer, an upper face opposed to the lower face, and a side face different from the lower and upper faces, the insulating film being formed on the upper face of the first magnetic layer and serving as a channel; a second magnetic layer formed on the upper face of the insulating film and serving as the other one of the source and the drain; a gate electrode formed along the side face of the insulating film; and a gate insulating film located between the gate electrode and the side face of the insulating film.
    Type: Application
    Filed: June 18, 2012
    Publication date: March 28, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomoaki Inokuchi, Takao Marukame, Tetsufumi Tanamoto, Hideyuki Sugiyama, Mizue Ishikawa, Yoshiaki Saito
  • Publication number: 20130077388
    Abstract: One embodiment provides a magnetic memory element, including: a first ferromagnetic layer whose magnetization is variable; a second ferromagnetic layer which has a first band split into a valence band and a conduction band and a second band being continuous at least from the valence band to the conduction band; and a nonmagnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer.
    Type: Application
    Filed: June 26, 2012
    Publication date: March 28, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Hideyuki Sugiyama, Masahiko Nakayama, Tatsuya Kishi, Hiroaki Yoda, Yoshiaki Saito
  • Patent number: 8405443
    Abstract: A pass transistor circuit according to an embodiment includes: a first input/output terminal connected to a first signal line; a second input/output terminal connected to a second signal line; a first device having a first terminal connected to a first power supply and a second terminal; a second device having a third terminal connected to the second terminal and a fourth terminal connected to a second power supply; a first transistor having one of source/drain connected to the second terminal, a gate receiving a first control signal; and a second transistor having a gate connected to the other one of source/drain of the first transistor, one of source/drain connected to the first input/output terminal, and the other one of source/drain connected to the second input/output terminal. One of the first and second devices is a nonvolatile memory device, the other one of the first and second devices is a MOSFET.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: March 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Sugiyama, Tetsufumi Tanamoto, Takao Marukame, Mizue Ishikawa, Tomoaki Inokuchi, Yoshiaki Saito
  • Patent number: 8385114
    Abstract: Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: February 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Sugiyama, Tetsufumi Tanamoto, Takao Marukame, Mizue Ishikawa, Tomoaki Inokuchi, Yoshiaki Saito
  • Patent number: 8373437
    Abstract: A look-up table circuit according to an embodiment includes: a variable resistance circuit including variable resistance devices and selecting a variable resistance device from the variable resistance devices based on an input signal; a reference circuit having a resistance value between the largest resistance value and the smallest resistance value of the variable resistance circuit; a first n-channel MOSFET including a source connected to a terminal of the variable resistance circuit and a gate connected to a drain; a second n-channel MOSFET including a source connected to a terminal of the reference circuit and a gate connected to the gate of the first n-channel MOSFET; a first current supply circuit to supply a current to the variable resistance circuit; a second current supply circuit to supply a current to the reference circuit; and a comparator comparing voltages at a first input terminal and a second input terminal.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: February 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Sugiyama, Tetsufumi Tanamoto, Takao Marukame, Mizue Ishikawa, Tomoaki Inokuchi, Yoshiaki Saito
  • Patent number: 8357962
    Abstract: A spin transistor includes a source electrode, a drain electrode, and a gate electrode on a semiconductor substrate. At least one of the source electrode and the drain electrode includes a semiconductor region and a magnetic layer. The semiconductor region is formed in the semiconductor substrate. The magnetic layer is formed on the semiconductor region, and contains a crystalline Heusler alloy containing at least one of cobalt (Co) and iron (Fe). The semiconductor region and the magnetic layer contain the same impurity element.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: January 22, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Marukame, Mizue Ishikawa, Tomoaki Inokuchi, Hideyuki Sugiyama, Yoshiaki Saito
  • Patent number: 8335059
    Abstract: A magnetoresistive effect element includes a first ferromagnetic layer, Cr layer, Heusler alloy layer, barrier layer, and second ferromagnetic layer. The first ferromagnetic layer has the body-centered cubic lattice structure. The Cr layer is formed on the first ferromagnetic layer and has the body-centered cubic lattice structure. The Heusler alloy layer is formed on the Cr layer. The barrier layer is formed on the Heusler alloy layer. The second ferromagnetic layer is formed on the barrier layer.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: December 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mizue Ishikawa, Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi
  • Patent number: 8330196
    Abstract: A semiconductor device according to an embodiment includes: a semiconductor layer; source and drain regions in the semiconductor layer; a magnetic metal semiconductor compound film on each of the source and drain regions, the magnetic metal semiconductor compound film including the same semiconductor as a semiconductor of the semiconductor layer and a magnetic metal; a gate insulating film on the semiconductor layer between the source region and the drain region; a gate electrode on the gate insulating film; a gate sidewall formed at a side portion of the gate electrode, the gate sidewall being made of an insulating material; a film stack formed on the magnetic metal semiconductor compound film on each of the source and drain regions, the film stack including a magnetic layer; and an oxide layer formed on the gate sidewall, the oxide layer containing the same element as an element in the film stack.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: December 11, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Marukame, Mizue Ishikawa, Tomoaki Inokuchi, Hideyuki Sugiyama, Yoshiaki Saito
  • Publication number: 20120273856
    Abstract: A magnetoresistive effect element includes a first ferromagnetic layer, Cr layer, Heusler alloy layer, barrier layer, and second ferromagnetic layer. The first ferromagnetic layer has the body-centered cubic lattice structure. The Cr layer is formed on the first ferromagnetic layer and has the body-centered cubic lattice structure. The Heusler alloy layer is formed on the Cr layer. The barrier layer is formed on the Heusler alloy layer. The second ferromagnetic layer is formed on the barrier layer.
    Type: Application
    Filed: June 26, 2012
    Publication date: November 1, 2012
    Inventors: Mizue ISHIKAWA, Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi
  • Publication number: 20120250399
    Abstract: A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode.
    Type: Application
    Filed: February 23, 2012
    Publication date: October 4, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideyuki SUGIYAMA, Masato ODA, Shinobu FUJITA, Tetsufumi TANAMOTO, Mizue ISHIKAWA, Takao MARUKAME, Tomoaki INOKUCHI, Yoshiaki SAITO
  • Publication number: 20120223762
    Abstract: A pass transistor circuit according to an embodiment includes: a first input/output terminal connected to a first signal line; a second input/output terminal connected to a second signal line; a first device having a first terminal connected to a first power supply and a second terminal; a second device having a third terminal connected to the second terminal and a fourth terminal connected to a second power supply; a first transistor having one of source/drain connected to the second terminal, a gate receiving a first control signal; and a second transistor having a gate connected to the other one of source/drain of the first transistor, one of source/drain connected to the first input/output terminal, and the other one of source/drain connected to the second input/output terminal. One of the first and second devices is a nonvolatile memory device, the other one of the first and second devices is a MOSFET.
    Type: Application
    Filed: March 14, 2012
    Publication date: September 6, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Sugiyama, Tetsufumi Tanamoto, Takao Marukame, Mizue Ishikawa, Tomoaki Inokuchi, Yoshiaki Saito
  • Publication number: 20120218802
    Abstract: One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected in parallel with the first spin MOSFET; a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET.
    Type: Application
    Filed: February 23, 2012
    Publication date: August 30, 2012
    Inventors: Takao MARUKAME, Tomoaki INOKUCHI, Hideyuki SUGIYAMA, Mizue ISHIKAWA, Yoshiaki SAITO, Atsuhiro KINOSHITA, Kosuke TATSUMURA
  • Patent number: 8243400
    Abstract: A magnetoresistive effect element includes a first ferromagnetic layer, Cr layer, Heusler alloy layer, barrier layer, and second ferromagnetic layer. The first ferromagnetic layer has the body-centered cubic lattice structure. The Cr layer is formed on the first ferromagnetic layer and has the body-centered cubic lattice structure. The Heusler alloy layer is formed on the Cr layer. The barrier layer is formed on the Heusler alloy layer. The second ferromagnetic layer is formed on the barrier layer.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: August 14, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mizue Ishikawa, Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi
  • Publication number: 20120168838
    Abstract: A semiconductor device according to an embodiment includes: a semiconductor layer; source and drain regions in the semiconductor layer; a magnetic metal semiconductor compound film on each of the source and drain regions, the magnetic metal semiconductor compound film including the same semiconductor as a semiconductor of the semiconductor layer and a magnetic metal; a gate insulating film on the semiconductor layer between the source region and the drain region; a gate electrode on the gate insulating film; a gate sidewall formed at a side portion of the gate electrode, the gate sidewall being made of an insulating material; a film stack formed on the magnetic metal semiconductor compound film on each of the source and drain regions, the film stack including a magnetic layer; and an oxide layer formed on the gate sidewall, the oxide layer containing the same element as an element in the film stack.
    Type: Application
    Filed: March 14, 2012
    Publication date: July 5, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao MARUKAME, Mizue Ishikawa, Tomoaki Inokuchi, Hideyuki Sugiyama, Yoshiaki Saito
  • Publication number: 20120119274
    Abstract: Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.
    Type: Application
    Filed: January 30, 2012
    Publication date: May 17, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Sugiyama, Tetsufumi Tanamoto, Takao Marukame, Mizue Ishikawa, Tomoaki Inokuchi, Yoshiaki Saito
  • Patent number: 8154916
    Abstract: Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: April 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Sugiyama, Tetsufumi Tanamoto, Takao Marukame, Mizue Ishikawa, Tomoaki Inokuchi, Yoshiaki Saito
  • Publication number: 20120074984
    Abstract: A look-up table circuit according to an embodiment includes: a variable resistance circuit including variable resistance devices and selecting a variable resistance device from the variable resistance devices based on an input signal; a reference circuit having a resistance value between the largest resistance value and the smallest resistance value of the variable resistance circuit; a first n-channel MOSFET including a source connected to a terminal of the variable resistance circuit and a gate connected to a drain; a second n-channel MOSFET including a source connected to a terminal of the reference circuit and a gate connected to the gate of the first n-channel MOSFET; a first current supply circuit to supply a current to the variable resistance circuit; a second current supply circuit to supply a current to the reference circuit; and a comparator comparing voltages at a first input terminal and a second input terminal.
    Type: Application
    Filed: September 21, 2011
    Publication date: March 29, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideyuki SUGIYAMA, Tetsufumi Tanamoto, Takao Marukame, Mizue Ishikawa, Tomoaki Inokuchi, Yoshiaki Saito
  • Patent number: 8139403
    Abstract: Certain embodiments provide a spin memory including a memory cell including a ferromagnetic stacked film that has a stacked structure in which a first ferromagnetic layer, a first nonmagnetic layer, a second ferromagnetic layer, a second nonmagnetic layer, and a third ferromagnetic layer are stacked in this order or reverse order, the third ferromagnetic layer and the second ferromagnetic layer being antiferromagnetically exchange-coupled via the second nonmagnetic layer. The ferromagnetic stacked film includes a current path in which a first and second write currents flow from the first ferromagnetic layer to the third ferromagnetic layer to write a first and second magnetization states into the first ferromagnetic layer respectively, and the second write current is higher than the first write current.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: March 20, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Hideyuki Sugiyama, Hisanori Aikawa, Masahiko Nakayama, Tatsuya Kishi, Hiroaki Yoda, Yoshiaki Saito