Patents by Inventor Mizue Ishikawa

Mizue Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8111087
    Abstract: A semiconductor integrated circuit includes an n-channel spin FET including one of a magnetic tunnel junction and a magneto-semiconductor junction, the n-channel spin FET including a gate terminal to receive an input signal, a source terminal to receive a first power supply potential, and a drain terminal connected to an output terminal, a p-channel FET including a gate terminal to receive a clock signal, a source terminal to receive a second power supply potential, and a drain terminal connected to the output terminal, a subsequent circuit connected to the output terminal, and a control circuit which turns on the p-channel FET to start charging the output terminal, then turns off the p-channel FET to end the charging, and supplies the input signal to the gate terminal of the n-channel spin FET.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: February 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoaki Inokuchi, Mizue Ishikawa, Hideyuki Sugiyama, Yoshiaki Saito
  • Publication number: 20120019283
    Abstract: A spin MOSFET includes: a first ferromagnetic layer provided on a semiconductor substrate, and having a fixed magnetization direction perpendicular to a film plane; a semiconductor layer provided on the first ferromagnetic layer, including a lower face opposed to the upper face of the first ferromagnetic layer, an upper face opposed to the lower face, and side faces different from the lower and upper faces; a second ferromagnetic layer provided on the upper face of the semiconductor layer, and having a variable magnetization direction perpendicular to a film plane; a first tunnel barrier provided on the second ferromagnetic layer; a third ferromagnetic layer provided on the first tunnel barrier; a gate insulating film provided on the side faces of the semiconductor layer; and a gate electrode provided on the side faces of the semiconductor layer with the gate insulating film being interposed therebetween.
    Type: Application
    Filed: September 9, 2011
    Publication date: January 26, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki SAITO, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa
  • Patent number: 8026561
    Abstract: A spin MOSFET includes: a first ferromagnetic layer provided on an upper face of a semiconductor substrate, and having a fixed magnetization direction perpendicular to a film plane; a semiconductor layer provided on an upper face of the first ferromagnetic layer, including a lower face opposed to the upper face of the first ferromagnetic layer, an upper face opposed to the lower face, and side faces different from the lower face and the upper face; a second ferromagnetic layer provided on the upper face of the semiconductor layer, and having a variable magnetization direction perpendicular to a film plane; a first tunnel barrier provided on an upper face of the second ferromagnetic layer; a third ferromagnetic layer provided on an upper face of the first tunnel barrier; a gate insulating film provided on the side faces of the semiconductor layer; and a gate electrode provided on the side faces of the semiconductor layer with the gate insulating film being interposed therebetween.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: September 27, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa
  • Publication number: 20110228596
    Abstract: Certain embodiments provide a spin memory including a memory cell including a ferromagnetic stacked film that has a stacked structure in which a first ferromagnetic layer, a first nonmagnetic layer, a second ferromagnetic layer, a second nonmagnetic layer, and a third ferromagnetic layer are stacked in this order or reverse order, the third ferromagnetic layer and the second ferromagnetic layer being antiferromagnetically exchange-coupled via the second nonmagnetic layer. The ferromagnetic stacked film includes a current path in which a first and second write currents flow from the first ferromagnetic layer to the third ferromagnetic layer to write a first and second magnetization states into the first ferromagnetic layer respectively, and the second write current is higher than the first write current.
    Type: Application
    Filed: September 20, 2010
    Publication date: September 22, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Hideyuki Sugiyama, Hisanori Aikawa, Masahiko Nakayama, Tatsuya Kishi, Hiroaki Yoda, Yoshiaki Saito
  • Publication number: 20110194342
    Abstract: Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.
    Type: Application
    Filed: September 24, 2010
    Publication date: August 11, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki SUGIYAMA, Tetsufumi TANAMOTO, Takao MARUKAME, Mizue ISHIKAWA, Tomoaki INOKUCHI, Yoshiaki SAITO
  • Patent number: 7973351
    Abstract: A stack includes a crystalline MgO layer, crystalline Heusler alloy layer, and amorphous Heusler alloy layer. The crystalline Heusler alloy layer is provided on the MgO layer. The amorphous Heusler alloy layer is provided on the crystalline Heusler alloy layer.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: July 5, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Marukame, Mizue Ishikawa, Tomoaki Inokuchi, Hideyuki Sugiyama, Yoshiaki Saito
  • Patent number: 7956395
    Abstract: A spin transistor includes a first ferromagnetic layer provided on a substrate and having an invariable magnetization direction, a second ferromagnetic layer provided on the substrate apart from the first ferromagnetic layer in a first direction, and having a variable magnetization direction, a plurality of projecting semiconductor layers provided on the substrate to extend in the first direction, and sandwiched between the first ferromagnetic layer and the second ferromagnetic layer, a plurality of channel regions respectively provided in the projecting semiconductor layers, and a gate electrode provided on the channel regions.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: June 7, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoaki Inokuchi, Mizue Ishikawa, Hideyuki Sugiyama, Yoshiaki Saito
  • Patent number: 7943974
    Abstract: A spin MOS field effect transistor includes a source electrode and a drain electrode each having a structure obtained by stacking an impurity diffusion layer, a (001)-oriented MgO layer and a Heusler alloy. The impurity diffusion layer is formed in a surface region of a semiconductor layer. The (001)-oriented MgO layer is formed on the impurity diffusion layer. The Heusler alloy is formed on the MgO layer.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: May 17, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mizue Ishikawa, Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi
  • Publication number: 20100244897
    Abstract: A spin MOSFET includes: a first ferromagnetic layer provided on an upper face of a semiconductor substrate, and having a fixed magnetization direction perpendicular to a film plane; a semiconductor layer provided on an upper face of the first ferromagnetic layer, including a lower face opposed to the upper face of the first ferromagnetic layer, an upper face opposed to the lower face, and side faces different from the lower face and the upper face; a second ferromagnetic layer provided on the upper face of the semiconductor layer, and having a variable magnetization direction perpendicular to a film plane; a first tunnel barrier provided on an upper face of the second ferromagnetic layer; a third ferromagnetic layer provided on an upper face of the first tunnel barrier; a gate insulating film provided on the side faces of the semiconductor layer; and a gate electrode provided on the side faces of the semiconductor layer with the gate insulating film being interposed therebetween.
    Type: Application
    Filed: March 17, 2010
    Publication date: September 30, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa
  • Patent number: 7796423
    Abstract: It is made possible to provide a reconfigurable logic circuit with which high integration can be achieved. A reconfigurable logic circuit includes: a multiplexer which includes a plurality of spin MOSFETs each having a source and drain containing a magnetic material, and a selecting portion including a plurality of MOSFETs and selecting a spin MOSFET from the plurality of spin MOSFETs, based on control data transmitted from control lines; a determining circuit which determines whether magnetization of the magnetic material of the source and drain of a selected spin MOSFET, which is selected by the selecting portion, is in a first state or in a second state; and a first and second write circuits which put the magnetization of the magnetic material of the source and drain of the selected spin MOSFET into the second and first states respectively by supplying a write current flowing between the source and drain of the selected spin MOSFET.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: September 14, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Sugiyama, Mizue Ishikawa, Tomoaki Inokuchi, Yoshiaki Saito, Tetsufumi Tanamoto
  • Publication number: 20100200899
    Abstract: A spin transistor includes a source electrode, a drain electrode, and a gate electrode on a semiconductor substrate. At least one of the source electrode and the drain electrode includes a semiconductor region and a magnetic layer. The semiconductor region is formed in the semiconductor substrate. The magnetic layer is formed on the semiconductor region, and contains a crystalline Heusler alloy containing at least one of cobalt (Co) and iron (Fe). The semiconductor region and the magnetic layer contain the same impurity element.
    Type: Application
    Filed: February 5, 2010
    Publication date: August 12, 2010
    Inventors: Takao MARUKAME, Mizue Ishikawa, Tomoaki Inokuchi, Hideyuki Sugiyama, Yoshiaki Saito
  • Publication number: 20100187585
    Abstract: A spin MOS field effect transistor includes a source electrode and a drain electrode each having a structure obtained by stacking an impurity diffusion layer, a (001)-oriented MgO layer and a Heusler alloy. The impurity diffusion layer is formed in a surface region of a semiconductor layer. The (001)-oriented MgO layer is formed on the impurity diffusion layer. The Heusler alloy is formed on the MgO layer.
    Type: Application
    Filed: March 31, 2010
    Publication date: July 29, 2010
    Inventors: Mizue Ishikawa, Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi
  • Patent number: 7709867
    Abstract: A spin MOS field effect transistor includes a source electrode and a drain electrode each having a structure obtained by stacking an impurity diffusion layer, a (001)-oriented MgO layer and a Heusler alloy. The impurity diffusion layer is formed in a surface region of a semiconductor layer. The (001)-oriented MgO layer is formed on the impurity diffusion layer. The Heusler alloy is formed on the MgO layer.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: May 4, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mizue Ishikawa, Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi
  • Publication number: 20100072528
    Abstract: A spin transistor includes a first ferromagnetic layer, a second ferromagnetic layer, a semiconductor layer between the first and second ferromagnetic layers, and a gate electrode on or above a surface of the semiconductor layer, the surface being between the first and second ferromagnetic layers. The first ferromagnetic layer comprises a ferromagnet which has a first minority spin band located at a high energy side and a second minority spin band located at a low energy side, and has a Fermi level in an area of the high energy side higher than a middle of a gap between the first and second minority spin bands.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 25, 2010
    Inventors: Tomoaki INOKUCHI, Takao Marukame, Mizue Ishikawa, Hideyuki Sugiyama, Yoshiaki Saito
  • Publication number: 20100072529
    Abstract: A stack includes a crystalline MgO layer, crystalline Heusler alloy layer, and amorphous Heusler alloy layer. The crystalline Heusler alloy layer is provided on the MgO layer. The amorphous Heusler alloy layer is provided on the crystalline Heusler alloy layer.
    Type: Application
    Filed: September 23, 2009
    Publication date: March 25, 2010
    Inventors: Takao MARUKAME, Mizue ISHIKAWA, Tomoaki INOKUCHI, Hideyuki SUGIYAMA, Yoshiaki SAITO
  • Publication number: 20100019798
    Abstract: It is made possible to provide a spin MOSFET that can minimize the increase in production costs and can perform both spin injection writing and reading. A spin MOSFET includes: a substrate that has a semiconductor region of a first conductivity type; first and second ferromagnetic stacked films that are formed at a distance from each other on the semiconductor region, and each have the same stacked structure comprising a first ferromagnetic layer, a nonmagnetic layer, and a second ferromagnetic layer stacked in this order, the second ferromagnetic stacked film having a film-plane area different from that of the first ferromagnetic stacked film; a gate insulating film that is formed on a portion of the semiconductor region, the portion being located between the first ferromagnetic stacked film and the second ferromagnetic stacked film; and a gate that is formed on the gate insulating film.
    Type: Application
    Filed: June 18, 2009
    Publication date: January 28, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi, Mizue Ishikawa, Takao Marukame
  • Publication number: 20090243653
    Abstract: A semiconductor integrated circuit includes an n-channel spin FET including one of a magnetic tunnel junction and a magneto-semiconductor junction, the n-channel spin FET including a gate terminal to receive an input signal, a source terminal to receive a first power supply potential, and a drain terminal connected to an output terminal, a p-channel FET including a gate terminal to receive a clock signal, a source terminal to receive a second power supply potential, and a drain terminal connected to the output terminal, a subsequent circuit connected to the output terminal, and a control circuit which turns on the p-channel FET to start charging the output terminal, then turns off the p-channel FET to end the charging, and supplies the input signal to the gate terminal of the n-channel spin FET.
    Type: Application
    Filed: March 23, 2009
    Publication date: October 1, 2009
    Inventors: Tomoaki INOKUCHI, Mizue Ishikawa, Hideyuki Sugiyama, Yoshiaki Saito
  • Publication number: 20090179667
    Abstract: It is made possible to provide a reconfigurable logic circuit with which high integration can be achieved. A reconfigurable logic circuit includes: a multiplexer which includes a plurality of spin MOSFETs each having a source and drain containing a magnetic material, and a selecting portion including a plurality of MOSFETs and selecting a spin MOSFET from the plurality of spin MOSFETs, based on control data transmitted from control lines; a determining circuit which determines whether magnetization of the magnetic material of the source and drain of a selected spin MOSFET, which is selected by the selecting portion, is in a first state or in a second state; and a first and second write circuits which put the magnetization of the magnetic material of the source and drain of the selected spin MOSFET into the second and first states respectively by supplying a write current flowing between the source and drain of the selected spin MOSFET.
    Type: Application
    Filed: December 19, 2008
    Publication date: July 16, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki SUGIYAMA, Mizue ISHIKAWA, Tomoaki INOKUCHI, Yoshiaki SAITO, Tetsufumi TANAMOTO
  • Publication number: 20090180215
    Abstract: A magnetoresistive effect element includes a first ferromagnetic layer, Cr layer, Heusler alloy layer, barrier layer, and second ferromagnetic layer. The first ferromagnetic layer has the body-centered cubic lattice structure. The Cr layer is formed on the first ferromagnetic layer and has the body-centered cubic lattice structure. The Heusler alloy layer is formed on the Cr layer. The barrier layer is formed on the Heusler alloy layer. The second ferromagnetic layer is formed on the barrier layer.
    Type: Application
    Filed: December 23, 2008
    Publication date: July 16, 2009
    Inventors: Mizue ISHIKAWA, Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi
  • Publication number: 20090059659
    Abstract: A spin transistor includes a first ferromagnetic layer provided on a substrate and having an invariable magnetization direction, a second ferromagnetic layer provided on the substrate apart from the first ferromagnetic layer in a first direction, and having a variable magnetization direction, a plurality of projecting semiconductor layers provided on the substrate to extend in the first direction, and sandwiched between the first ferromagnetic layer and the second ferromagnetic layer, a plurality of channel regions respectively provided in the projecting semiconductor layers, and a gate electrode provided on the channel regions.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 5, 2009
    Inventors: Tomoaki INOKUCHI, Mizue Ishikawa, Hideyuki Sugiyama, Yoshiaki Saito