Patents by Inventor Mizue Ishikawa

Mizue Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090057654
    Abstract: A spin FET of an aspect of the present invention includes source/drain regions, a channel region between the source/drain regions, and a gate electrode above the channel region. Each of the source/drain regions includes a stack structure which is comprised of a low work function material and a ferromagnet. The low work function material is a non-oxide which is comprised of one of Mg, K, Ca and Sc, or an alloy which includes the non-oxide of 50 at % or more.
    Type: Application
    Filed: August 25, 2008
    Publication date: March 5, 2009
    Inventors: Yoshiaki SAITO, Hideyuki Sugiyama, Tomoaki Inokuchi, Mizue Ishikawa
  • Publication number: 20090050948
    Abstract: A spin MOS field effect transistor includes a source electrode and a drain electrode each having a structure obtained by stacking an impurity diffusion layer, a (001)-oriented MgO layer and a Heusler alloy. The impurity diffusion layer is formed in a surface region of a semiconductor layer. The (001)-oriented MgO layer is formed on the impurity diffusion layer. The Heusler alloy is formed on the MgO layer.
    Type: Application
    Filed: August 20, 2008
    Publication date: February 26, 2009
    Inventors: Mizue ISHIKAWA, Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi