Abstract: A power transfer device includes an oscillator circuit having a first node, a second node, and a control terminal. The oscillator circuit includes a cascode circuit comprising transistors having a first conductivity type and a first breakdown voltage. The cascode circuit is coupled to the control terminal, the first node, and the second node. The oscillator circuit includes a latch circuit coupled between the cascode circuit and a first power supply node. The latch circuit includes cross-coupled transistors having the first conductivity type and a second breakdown voltage. The first breakdown voltage is greater than the second breakdown voltage. The oscillator circuit may be configured to develop a pseudo-differential signal on the first node and the second node. The pseudo-differential signal may have a peak voltage of at least three times a voltage level of an input DC signal on a second power supply node.

Abstract: A technique for attenuating common mode transient events uses a differential receiver circuit including a band-stop filter having a stopband fSB around a notch frequency fn of a received signal. The differential receiver circuit includes a first high-pass filter coupled in series with the band-stop filter. The notch frequency fn is less than a carrier frequency fc of a signal received by the differential receiver circuit. The band-stop filter may include a buffer circuit and a notch filter coupled in series with the buffer circuit. The notch filter may have a second stopband around the notch frequency fn. The differential receiver circuit may have a propagation delay that is independent of a pulse width of common mode transient energy attenuated by the differential receiver circuit.

Abstract: An isolated power transfer device has a primary side and a secondary side isolated from the primary side by an isolation barrier. A secondary-side circuit includes a rectifier circuit coupled to a secondary-side conductive coil. The secondary-side circuit includes a first resistor coupled to a first power supply node and a terminal node. The secondary-side circuit includes a second resistor coupled to the terminal node and a second power supply node. The secondary-side circuit includes a first circuit to generate a feedback signal in response to a reference voltage and a signal on the terminal node. The feedback signal has a hysteretic band defined by the first resistor and the second resistor. The secondary-side circuit is configured as an AC/DC power converter that provides, on the first power supply node, an output DC signal having a voltage level based on a ratio of the first resistor to the second resistor.

Abstract: An isolated power transfer device has a primary side and a secondary side isolated from the primary side by an isolation barrier. A secondary-side circuit includes a rectifier circuit coupled to a secondary-side conductive coil. The secondary-side circuit includes a first resistor coupled to a first power supply node and a terminal node. The secondary-side circuit includes a second resistor coupled to the terminal node and a second power supply node. The secondary-side circuit includes a first circuit to generate a feedback signal in response to a reference voltage and a signal on the terminal node. The feedback signal has a hysteretic band defined by the first resistor and the second resistor. The secondary-side circuit is configured as an AC/DC power converter that provides, on the first power supply node, an output DC signal having a voltage level based on a ratio of the first resistor to the second resistor.

Abstract: A power transfer device includes an oscillator circuit having a first node, a second node, and a control terminal. The oscillator circuit includes a cascode circuit comprising transistors having a first conductivity type and a first breakdown voltage. The cascode circuit is coupled to the control terminal, the first node, and the second node. The oscillator circuit includes a latch circuit coupled between the cascode circuit and a first power supply node. The latch circuit includes cross-coupled transistors having the first conductivity type and a second breakdown voltage. The first breakdown voltage is greater than the second breakdown voltage. The oscillator circuit may be configured to develop a pseudo-differential signal on the first node and the second node. The pseudo-differential signal may have a peak voltage of at least three times a voltage level of an input DC signal on a second power supply node.

Abstract: A semiconductor device includes a first a first transistor configured to operate at a first threshold voltage level. The first transistor includes a first gate structure and a first drain terminal electrically coupled to the first gate structure. The semiconductor device also includes a second transistor configured to operate at a second threshold voltage level different from the first threshold voltage level. The second transistor includes a second source terminal and a second gate structure electrically coupled to the first gate structure. The first gate structure and the second gate structure comprise a first component in common, and the second gate structure further includes at least one extra component disposed over the first component. The number of the at least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.

Abstract: A voltage reference includes a flipped gate transistor and a first transistor, the first transistor having a first leakage current, wherein the first transistor is connected with the flipped gate transistor in a Vgs subtractive arrangement. The voltage reference further includes an output node configured to output a reference voltage, the output node connected to the first transistor. The voltage reference further includes a second transistor connected to the output node, the second transistor having a second leakage current. The voltage reference further includes a boxing region configured to provide a voltage level at a drain terminal of the first transistor to maintain the first leakage current substantially equal to the second leakage current.

Abstract: A voltage reference includes a flipped gate transistor coupled between a first node configured to carry an operating voltage and a second node configured to carry a negative supply voltage. A first transistor and a second transistor are coupled in series between the first node and the second node, a gate of the first transistor is coupled with a gate of the flipped gate transistor, and a gate of the second transistor is configured to receive the negative supply voltage. An output node between the first transistor and the second transistor is configured to output a reference voltage, and a current source coupled between the output node and the second node is configured to supply a current through the first transistor based on a current through the flipped gate transistor.

Abstract: A technique for attenuating common mode transient events uses a differential receiver circuit including a band-stop filter having a stopband fSB around a notch frequency fn of a received signal. The differential receiver circuit includes a first high-pass filter coupled in series with the band-stop filter. The notch frequency fn is less than a carrier frequency fc of a signal received by the differential receiver circuit. The band-stop filter may include a buffer circuit and a notch filter coupled in series with the buffer circuit. The notch filter may have a second stopband around the notch frequency fn. The differential receiver circuit may have a propagation delay that is independent of a pulse width of common mode transient energy attenuated by the differential receiver circuit.

Abstract: A start-up circuit includes an input node, an output node, a reference node, and a depletion mode field-effect transistor (FET) having a first terminal coupled to the input node, a second terminal coupled to the output node, and a gate terminal. A Zener diode has a cathode coupled to the gate terminal of the FET and an anode coupled to the reference node. A first capacitor is coupled in parallel with the Zener diode, a first resistor is coupled between the gate terminal of the FET and the input node, and a second resistor is coupled between the second terminal of the FET and the reference node. The FET and the second resistor are configured to generate an output voltage on the output node, the output voltage being based on an input voltage on the input node and capped at a value below a peak value of the input voltage.

Abstract: A semiconductor device includes a first a first transistor configured to operate at a first threshold voltage level. The first transistor includes a first gate structure and a first drain terminal electrically coupled to the first gate structure. The semiconductor device also includes a second transistor configured to operate at a second threshold voltage level different from the first threshold voltage level, The second transistor includes a second source terminal and a second gate structure electrically coupled to the first gate structure. The first gate structure and the second gate structure comprise a first component in common, and the second gate structure further includes at least one extra component disposed over the first component. The number of the at least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.

Abstract: A current reference comprising: a control resistor; a tracking voltage generator including: a first, flipped gate transistor having a first size; and a second transistor having a second size; wherein the tracking voltage generator is configured to output a tracking voltage having a first temperature dependency based on a ratio of the second size to the first size, the temperature dependency thereby being substantially equal to a second temperature dependency of the control resistor; and an amplifier circuit configured to receive the tracking voltage and maintain a voltage at a first terminal of the control resistor, the voltage being substantially equal to the tracking voltage; wherein the current reference thereby is configured to maintain a reference current through the control resistor at a constant value.

Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first transistor configured to include a first threshold voltage level. The first transistor includes a gate structure. The gate structure includes a first component including a first conductive type. A second transistor configures to include a second threshold voltage level different from the first threshold voltage level. The second transistor includes a gate structure. The gate structure includes a second component including the first conductive type. At least one extra component is disposed over the second component. The least one extra component includes a second conductive type opposite to the first conductive type. The first transistor and the second transistor are coupled such that the number of the least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.

Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first transistor configured to include a first threshold voltage level. The first transistor includes a gate structure. The gate structure includes a first component including a first conductive type. A second transistor configures to include a second threshold voltage level different from the first threshold voltage level. The second transistor includes a gate structure. The gate structure includes a second component including the first conductive type. At least one extra component is disposed over the second component. The least one extra component includes a second conductive type opposite to the first conductive type. The first transistor and the second transistor are coupled such that the number of the least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.

Abstract: A current reference includes a tracking voltage generator. The tracking voltage generator includes a flipped gate transistor and a first transistor, the first transistor having a first leakage current, wherein the first transistor is connected with the flipped gate transistor in a Vgs subtractive arrangement. The tracking voltage generator further includes an output node configured to output a tracking voltage; and a second transistor connected to the output node, the second transistor having a second leakage current. The current reference further includes an amplifier configured to receive the tracking voltage and to output an amplified signal. The current reference further includes a control transistor configured to receive the amplified signal and to conduct a reference current therethrough. The current reference further includes a control resistor connected in series with the control transistor.

Abstract: For starting-up a power converter, an AC rectified voltage is generated upon power-up of the power converter. A depletion mode transistor generates a first voltage from the rectified voltage. The first voltage is inputted to a controller of the power converter to provide power for operation of the controller before an output stage of the power converter starts outputting power. A gate biasing voltage is generated from the first voltage and supplied to a gate terminal of the depletion mode transistor to bias the gate terminal of the depletion mode transistor.

Abstract: A start-up circuit includes an input node, an output node, a reference node, and a depletion mode field-effect transistor (FET) having a first terminal coupled to the input node, a second terminal coupled to the output node, and a gate terminal. A Zener diode has a cathode coupled to the gate terminal of the FET and an anode coupled to the reference node. A first capacitor is coupled in parallel with the Zener diode, a first resistor is coupled between the gate terminal of the FET and the input node, and a second resistor is coupled between the second terminal of the FET and the reference node. The FET and the second resistor are configured to generate an output voltage on the output node, the output voltage being based on an input voltage on the input node and capped at a value below a peak value of the input voltage.

Abstract: An AC-DC power converter includes a rectifying unit for generating a rectified voltage, an output stage for converting the rectified voltage into a DC voltage for a load, a controller for controlling the output stage, and a start-up circuit. The start-up circuit includes a start-up voltage generator coupled to the rectifying unit and configured to generate a start-up voltage from the rectified voltage and to output the start-up voltage to the controller to provide power for operation of the controller before the output stage starts outputting power. The start-up voltage generator includes a first depletion mode transistor having a first terminal configured to receive the rectified voltage, a second terminal configured to output at least partially the start-up voltage, and a gate terminal which is grounded.

Abstract: An AC-DC power converter includes a rectifying unit for generating a rectified voltage, an output stage for converting the rectified voltage into a DC voltage for a load, a controller for controlling the output stage, and a start-up circuit. The start-up circuit includes a first power section coupled to the rectifying unit and configured to generate a first voltage from the rectified voltage and to output the first voltage to the controller to enable the controller before the output stage starts outputting power. The first power section includes a depletion mode transistor having a first terminal configured to receive the rectified voltage and a second terminal configured to output the first voltage.

Abstract: An AC-DC power converter includes a rectifying unit, an output stage, a controller and a soft-start circuit. The rectifying unit is configured to rectify an AC voltage to a rectified voltage. The output stage is coupled to the rectifying unit and configured to convert the rectified voltage into a DC voltage for a load. The controller is coupled to the output stage and configured to control the output stage. The soft-start circuit is coupled to the rectifying unit to receive the rectified voltage. The soft-start circuit is configured to detect whether the rectified voltage is at or below a predetermined level, and to enable the controller if the rectified voltage is detected to be at or below the predetermined level.