Abstract: A current reference includes a tracking voltage generator. The tracking voltage generator includes a flipped gate transistor and a first transistor, the first transistor having a first leakage current, wherein the first transistor is connected with the flipped gate transistor in a Vgs subtractive arrangement. The tracking voltage generator further includes an output node configured to output a tracking voltage; and a second transistor connected to the output node, the second transistor having a second leakage current. The current reference further includes an amplifier configured to receive the tracking voltage and to output an amplified signal. The current reference further includes a control transistor configured to receive the amplified signal and to conduct a reference current therethrough. The current reference further includes a control resistor connected in series with the control transistor.

Abstract: A voltage reference includes a flipped gate transistor configured to receive a first current. The voltage reference further includes a first transistor configured to receive a second current, the first transistor having a first leakage current, wherein the first transistor is connected with the flipped gate transistor in a Vgs subtractive arrangement. The voltage reference further includes an output node configured to output a reference voltage, the output node connected to the first transistor. The voltage reference further includes a second transistor connected to the output node, the second transistor having a second leakage current, wherein the first leakage current is substantially equal to the second leakage current.

Abstract: A voltage reference includes a flipped gate transistor and a first transistor, the first transistor having a first leakage current, wherein the first transistor is connected with the flipped gate transistor in a Vgs subtractive arrangement. The voltage reference further includes an output node configured to output a reference voltage, the output node connected to the first transistor. The voltage reference further includes a second transistor connected to the output node, the second transistor having a second leakage current. The voltage reference further includes a boxing region configured to provide a voltage level at a drain terminal of the first transistor to maintain the first leakage current substantially equal to the second leakage current.

Abstract: For starting-up a power converter, an AC rectified voltage is generated upon power-up of the power converter. A depletion mode transistor generates a first voltage from the rectified voltage. The first voltage is inputted to a controller of the power converter to provide power for operation of the controller before an output stage of the power converter starts outputting power. A gate biasing voltage is generated from the first voltage and supplied to a gate terminal of the depletion mode transistor to bias the gate terminal of the depletion mode transistor.

Abstract: An AC-DC power converter includes a rectifying unit for generating a rectified voltage, an output stage for converting the rectified voltage into a DC voltage for a load, a controller for controlling the output stage, and a start-up circuit. The start-up circuit includes a first power section coupled to the rectifying unit and configured to generate a first voltage from the rectified voltage and to output the first voltage to the controller to enable the controller before the output stage starts outputting power. The first power section includes a depletion mode transistor having a first terminal configured to receive the rectified voltage and a second terminal configured to output the first voltage.

Abstract: One embodiment of the invention includes a regulator circuit that regulates a substantially constant magnitude of an output voltage at an output node. The circuit includes a master stage configured to set a first threshold voltage and a second threshold voltage. The first threshold voltage can have a magnitude that is greater than the second threshold voltage. The circuit also includes a charging follower stage configured to conduct a first current from a first power rail to the output node. The first current can increase in response to a transient decrease of the output voltage relative to the first threshold voltage. The circuit further includes a discharging follower stage configured to conduct a second current from the output node to a second power rail. The second current can increase in response to a transient increase of the output voltage relative to the second threshold voltage.

Abstract: Multistage charge pumps with diode loss compensation are disclosed. In one example, a pre-regulated charge pump to generate a voltage is described. The example pre-regulated charge pump includes a charge pump having a plurality of stages and one or more diodes. The stages are configured to generate an output voltage at an output terminal based on an input voltage and a number of the multiplier stages. The example pre-regulated charge pump also includes a pre-regulator stage configured to adjust the input voltage to remove dependency on supply voltage variation. The pre-regulator includes a feedback diode configured to compensate for one or more voltage drops associated with the one or more charge pump diodes.

Abstract: One embodiment of the invention includes a level-shifter circuit. The circuit comprises a control stage that steers a current from one of a first control node and a second control node to the other of the first control node and the second control node based on an input signal to set a first initial voltage at the first control node and a second initial voltage at the second control node, the input signal having logic-high and logic-low voltage magnitudes that occupy a low voltage domain. The circuit also includes a logic driver that is coupled to the second control node and is referenced in a high voltage domain. The logic driver can be configured to provide an output signal having logic-high and logic-low voltage magnitudes that occupy the high voltage domain based on the second initial voltage.

Abstract: Embodiments of the present disclosure provide a fault protection circuit, a method of operating a fault protection circuit and a voltage regulator. In one embodiment, the fault protection circuit is for use with the voltage regulator and includes an output power section having first and second MOS transistors configured to provide a regulated voltage on an output node of the voltage regulator. The fault protection circuit also includes a gate pull-down section connected to the first and second MOS transistors and configured to provide a gate pull-down MOS transistor to limit a current through the first and second MOS transistors during a current overload fault condition on the output node.

Abstract: A real time clock (RTC) voltage regulator, a method of regulating an RTC voltage and a power management integrated circuit (PMIC). In one embodiment, an RTC voltage regulator includes a current source configured to provide a first current and a voltage regulator having a common gate amplifier and a power device. The first current is employed to establish a reference voltage for the common gate amplifier and the common gate amplifier is configured to control the power device. The power device is configured to provide an RTC voltage for the common gate amplifier.

Abstract: One embodiment of the invention includes a regulator circuit that regulates a substantially constant magnitude of an output voltage at an output node. The circuit includes a master stage configured to set a first threshold voltage and a second threshold voltage. The first threshold voltage can have a magnitude that is greater than the second threshold voltage. The circuit also includes a charging follower stage configured to conduct a first current from a first power rail to the output node. The first current can increase in response to a transient decrease of the output voltage relative to the first threshold voltage. The circuit further includes a discharging follower stage configured to conduct a second current from the output node to a second power rail. The second current can increase in response to a transient increase of the output voltage relative to the second threshold voltage.

Abstract: One embodiment of the invention includes a level-shifter circuit. The circuit comprises a control stage that steers a current from one of a first control node and a second control node to the other of the first control node and the second control node based on an input signal to set a first initial voltage at the first control node and a second initial voltage at the second control node, the input signal having logic-high and logic-low voltage magnitudes that occupy a low voltage domain. The circuit also includes a logic driver that is coupled to the second control node and is referenced in a high voltage domain. The logic driver can be configured to provide an output signal having logic-high and logic-low voltage magnitudes that occupy the high voltage domain based on the second initial voltage.

Abstract: One embodiment of the present invention includes a system for providing a soft-start for a power regulator comprising a differential transistor pair that receives an input current and conducts a first current through a first transistor and a second current through a second transistor. One of the first and second current changes in response to a change in the other to maintain a sum of the first and second current being substantially equal to the input current. The system also comprises a comparator that provides an output signal based on a comparison of a first input voltage and a second input voltage associated with the first current and the second current, respectively. The system further comprises a current source activated by the output signal to charge a capacitor that increases a soft-start reference voltage associated with control of the power regulator and which controls the change in the other of the first and second current.

Abstract: One embodiment of the present invention includes a system for providing a soft-start for a power regulator comprising a differential transistor pair that receives an input current and conducts a first current through a first transistor and a second current through a second transistor. One of the first and second current changes in response to a change in the other to maintain a sum of the first and second current being substantially equal to the input current. The system also comprises a comparator that provides an output signal based on a comparison of a first input voltage and a second input voltage associated with the first current and the second current, respectively. The system further comprises a current source activated by the output signal to charge a capacitor that increases a soft-start reference voltage associated with control of the power regulator and which controls the change in the other of the first and second current.

Abstract: Multistage charge pumps with diode loss compensation are disclosed. In one example, a pre-regulated charge pump to generate a voltage is described. The example pre-regulated charge pump includes a charge pump having a plurality of stages and one or more diodes. The stages are configured to generate an output voltage at an output terminal based on an input voltage and a number of the multiplier stages. The example pre-regulated charge pump also includes a pre-regulator stage configured to adjust the input voltage to remove dependency on supply voltage variation. The pre-regulator includes a feedback diode configured to compensate for one or more voltage drops associated with the one or more charge pump diodes.

Abstract: Embodiments of the present disclosure provide a fault protection circuit, a method of operating a fault protection circuit and a voltage regulator. In one embodiment, the fault protection circuit is for use with the voltage regulator and includes an output power section having first and second MOS transistors configured to provide a regulated voltage on an output node of the voltage regulator. The fault protection circuit also includes a gate pull-down section connected to the first and second MOS transistors and configured to provide a gate pull-down MOS transistor to limit a current through the first and second MOS transistors during a current overload fault condition on the output node.

Abstract: A real time clock (RTC) voltage regulator, a method of regulating an RTC voltage and a power management integrated circuit (PMIC). In one embodiment, an RTC voltage regulator includes a current source configured to provide a first current and a voltage regulator having a common gate amplifier and a power device. The first current is employed to establish a reference voltage for the common gate amplifier and the common gate amplifier is configured to control the power device. The power device is configured to provide an RTC voltage for the common gate amplifier.

Abstract: Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with programmable hysteresis. Such circuits include a comparator input circuit that receives two inputs to be compared. The comparator input circuit provides a first differential current output based at least in part on a difference between the first voltage input and the second voltage input. The aforementioned circuits further include a hysteresis control circuit that is operable to receive a single programmable voltage input, and to provide a second differential current output based at least in part on the comparator output and the single programmable voltage input. An output circuit is also included that sums the first differential current and the second differential current, and provides a comparator output based at least in part on the sum of the first differential current and the second differential current.

Abstract: One embodiment of the present invention includes a system for providing a soft-start for a power regulator comprising a differential transistor pair that receives an input current and conducts a first current through a first transistor and a second current through a second transistor. One of the first and second current changes in response to a change in the other to maintain a sum of the first and second current being substantially equal to the input current. The system also comprises a comparator that provides an output signal based on a comparison of a first input voltage and a second input voltage associated with the first current and the second current, respectively. The system further comprises a current source activated by the output signal to charge a capacitor that increases a soft-start reference voltage associated with control of the power regulator and which controls the change in the other of the first and second current.

Abstract: Systems and methods are provided for providing precision timing signals. A first register bank, driven by a first clock signal, provides a first delay along a first signal path. A second register bank, driven by a second clock signal related to the first clock signal, provides a second delay along a second signal path. A system control controls at least one of the first and second banks of registers to control the first and second delays, as to provide a desired skew between the output of the first signal path and the second signal path.