Abstract: A flash memory device which comprises a memory cell array having memory cells arranged in rows and columns; a word line voltage generator circuit configured to generate a program voltage, a dielectric breakdown prevention voltage, and a pass voltage at a program operation; and a row selector circuit that receives the program voltage, the dielectric breakdown prevention voltage, and the pass voltage and selecting one of the rows in response to a row address. The dielectric breakdown prevention voltage is lower than the program voltage and higher than the pass voltage; and the row selector circuit drives the selected row with the program voltage, drives at least one row just adjacent to, or neighboring, the selected row with the dielectric breakdown prevention voltage and drives remaining rows with the pass voltage.

Abstract: A flash memory device which includes a memory cell array which stores data and trim information, and control logic which controls programming, erasing, and reading modes of the memory cell array. The control logic is operative to receive the trim information from the memory cell array in a power-up mode, and to optimize operational time periods of the programming, erasing, and reading modes in accordance with the trim information.

Abstract: A method of programming a flash memory includes programming memory cells connected to a selected word line by applying a first voltage to the selected word line and a second voltage to non-selected word lines, the second voltage being lower than the first voltage, lowering the first voltage of the selected word line to a third voltage after programming the memory cells connected to the selected word line, the third voltage being lower than the first voltage, and recovering a fourth voltage of the selected word line and the non-selected word lines, the fourth voltage being lower than the second and third voltages.

Abstract: Non-volatile memory devices and operating methods thereof are provided. In an operating method, a first operation is performed by applying a first voltage to at least one word line. The first operation includes one of a programming or erasing operation. The first operation is verified by applying a verify voltage to each of the at least one word lines. The voltage level of each verify voltage is determined according to position information of a corresponding one of the at least one word lines.

Abstract: A method of reading data of a multi-level cell (MLC) flash memory device is disclosed. The method includes reading a least significant bit (LSB) and a most significant bit (MSB) of the data programmed to a plurality of memory cells. Reading each of the LSB and MSB includes; reading a MSB flag indicating whether or not the MSB for memory cells in a page of memory cells has been programmed, performing a first read with respect to a plurality of first bit lines, setting a target voltage in view of the read value of the MSB flag, applying the target voltage to a plurality of second bit lines, and performing a second read with respect to the plurality of second bit lines.

Abstract: Described herein are Group 4 metal-containing precursors, compositions comprising Group 4 metal-containing precursors, and deposition processes for fabricating conformal metal containing films on substrates. In one aspect, the Group 4 metal-containing precursors are represented by the following formula I: wherein M comprises a metal chosen from Ti, Zr, and Hf; R and R1 are each independently selected from an alkyl group comprising from 1 to 10 carbon atoms; R2 is an alkyl group comprising from 1 to 10 carbon atoms; R3 is chosen from hydrogen or an alkyl group comprising from 1 to 3 carbon atoms; R4 is an alkyl group comprising from 1 to 6 carbon atoms and wherein R2 and R4 are different alkyl groups. Also described herein are methods for making Group 4 metal-containing precursors and methods for depositing films using the Group 4 metal-containing precursors.

Abstract: A NAND flash memory device and a programming method thereof capable of improving a program speed during a multi-level cell programming operation are provided. The device performs a programming operation using an ISPP method. Additionally, the device includes a memory cell storing multi-bit data; a program voltage generating circuit generating a program voltage to be supplied to the memory cell; and a program voltage controller controlling a start level of the program voltage. The device supplies an LSB start voltage to a selected word line during an LSB program, and an MSB start voltage higher than the LSB start voltage to the selected word line during an MSB program.

Abstract: Provided is a method of programming the flash memory device including setting increments of program voltages according to data states expressed as threshold voltage distributions of multi-level memory cells. An Increment Step Pulse Programming (ISPP) clock signal corresponds to a loop clock signal and the increments of the program voltages and is generated in response to program pass/fail information. A default level enable signal is generated by performing a counting operation until reaching the increments of the program voltages, in response to the loop clock signal. An additional level enable signal is generated by performing a counting operation until reaching the increments of the program voltages, in response to the ISPP clock signal. The program voltage is increased by 1 increment, in response to the default level enable signal. The program voltage is increased by 2 increments, in response to the additional level enable signal.

Abstract: A cyclic deposition process to make a metal oxide film on a substrate, which comprises the steps: introducing a metal ketoiminate into a deposition chamber and depositing the metal ketoiminate on a heated substrate; purging the deposition chamber to remove unreacted metal ketominate and any byproduct; introducing an oxygen-containing source to the heated substrate; purging the deposition chamber to remove any unreacted chemical and byproduct; and, repeating the cyclic deposition process until a desired thickness of film is established.

Abstract: A flash memory device is disclosed that comprises memory cells, a sense node connected to a selected bit line, a sense circuit configured to selectively provide a first voltage to a common node in accordance with a voltage level of the sense node, a first register connected to the sense node and the common node and configured to store data in accordance with a voltage level of the common node, a second register configured to store data in accordance with the voltage level of the sense node, a switch configured to provide a second voltage to the second register, and a discharge circuit configured to selectively discharge the sense node in accordance with the data stored in the second register.

Abstract: A flash memory device including a controller to determine higher, M, and lower, N, word-line address bits based on an input word-line address, to determine a selected area of a memory array based on the higher and lower word-line address bits, and an unselected area of the memory array based on the selected area; and a high voltage generator to provide a first pass voltage to a word line of the selected area, and to provide a second pass voltage to a word line of the unselected area. The pass voltages are discriminately applied to the programmed and non-programmed memory cells, enlarging the pass voltage window. The memory array is divided into pluralities of zones to which local voltages are each applied in different levels.

Abstract: The flash memory device includes a memory cell array having a plurality of memory cells, a high voltage generator configured to generate a plurality of pass voltages, with a first pass voltage of the plurality of pass voltages supplied to the memory cell array during a programming operation; and a main controller including a voltage controller configured to shift the first pass voltage at a plurality of time intervals during the programming operation.

Abstract: Disclosed is a flash memory device having multiple strings, where each string includes first memory cells and second memory cells. One second memory cell of the second memory cells in each string is set to a programmed state, and remaining second memory cells are set to an erased state.

Abstract: Provided is a method of programming the flash memory device including setting increments of program voltages according to data states expressed as threshold voltage distributions of multi-level memory cells. An Increment Step Pulse Programming (ISPP) clock signal corresponds to a loop clock signal and the increments of the program voltages and is generated in response to program pass/fail information. A default level enable signal is generated by performing a counting operation until reaching the increments of the program voltages, in response to the loop clock signal. An additional level enable signal is generated by performing a counting operation until reaching the increments of the program voltages, in response to the ISPP clock signal. The program voltage is increased by 1 increment, in response to the default level enable signal. The program voltage is increased by 2 increments, in response to the additional level enable signal.

Abstract: A flash memory device may include a memory cell array having a plurality of word lines, bit lines, and memory cells. Each memory cell may be arranged at an intersection of a corresponding word line and a corresponding bit line. The device may include a bit line voltage setting circuit for setting a voltage on a bit line of a given memory cell to be programmed to a variable bit line voltage or to a ground voltage. A variable bit line voltage generating circuit may be provided in the flash memory device for generating the variable bit line voltage. To facilitating programming of the device, a bit line voltage of a given memory cell to be programmed may be set based on a supply voltage of the device, so as to maintain a voltage difference based on the set bit line voltage above a given threshold voltage.

Abstract: Methods for the deposition via chemical vapor deposition or atomic layer deposition of metal containing films, such as, for example, metal silicate or metal silicon oxynitride films are described herein. In one embodiment, the method for depositing a metal-containing film comprises the steps of introducing into a reaction chamber, a metal amide precursor, a silicon-containing precursor, and an oxygen source wherein each precursor is introduced after introducing a purge gas.

Abstract: The invention provides a novel compound of Formula II which is useful in the preparation of imipenem monohydrate of Formula I, wherein R1 is a p-nitrobenzyl or p-methoxybenzyl group; and R2 and R3 may be identical to or different from each other and are each independently a C1-6alkyl or aryl group, or a derivative thereof, and a process for preparing the compound of Formula II by coupling (5R,6S) p-nitrobenzyl-3-(diphenylphosphono)-6-[(1R)-1-hydroxyethyl]-1-azabicyclo[3.2.0]hept-2-ene-7-one-2-carboxylate with 2-aminoetahnethiol hydrocloride in the presence of a base, followed by a reaction with a ketone. Further, the invention provides a process for preparing the compound of Formula I by reacting a compound of Formula II with isopropylformimidate or benzylformimidate in the presence of a base, followed by hydrogenation, separation and crystallization.

Abstract: Provided are a non-volatile memory device and a method of programming the same. The method includes: performing a program operation; performing a program verify read operation; and performing a pass/fail determine operation simultaneously with one of a verify recovery operation and a bit line setup operation, after the performing of the program verify read operation.

Abstract: Disclosed herein is a method for high-yield production of Schizophyllum commune-derived beta-glucan having a homogeneous composition, comprising subjecting mycelia of Schizophyllum commune to liquid culture with an addition of a synthetic adsorbent, and a composition for external application comprising the beta-glucan produced therefrom, which is capable of relieving dry skin conditions, atopic diseases and itching.

Abstract: A programming method of a multi-bit flash memory device includes programming multi-bit data into selected memory cells through pluralities of programming loops. In each programming loop, an increment of a programming voltage applied to the selected memory cells is varied in accordance with a result of program-verification for each data state of the multi-bit data and reading-verification for a data state is skipped when the program-verification indicates that data state has passed.