Abstract: A vehicle information system includes an image capturing module, configured to capture instant traffic images in front of a vehicle, and a dashboard, connected to the image capturing module, configured to present vehicle information concerning the vehicle and the instant traffic images. With the design of the vehicle information system, the driver will always stay alerts and be aware of the traffic condition even if his or her is looking down to the vehicle information presented on the dashboard.

Abstract: A headlight system includes a headlight module having at least one headlight device arranged on a vehicle and having a predefined illuminating range; a driving module having at least one driving unit configured to adjust the illuminating direction of the headlight device within the predefined illuminating range; a gaze detecting device detecting a driver's gaze direction; an input device receiving a direction adjusting command issued by the driver; and a control unit electrically connected to the driving module, the gaze detecting device and the input device, wherein when the input device receives the direction adjusting command from the driver, and the control unit determines whether the drivers' gaze direction falls within the predefined illuminating range; if so, the control unit controls the driving unit to adjust the illuminating direction of the headlight device toward the driver's gaze direction.

Abstract: A leak detection system, comprising a gas supplying device, configured to provide a tracer gas, wherein a temperature of the tracer gas is higher or lower than a temperature of ambient air; a gas pumping device, connected to the gas supplying device, configured to pump the tracer gas into a case; a gas exhausting device, configured to exhaust gas out of the case; a thermal image capturing device, configured to capture thermal images of the case; and a processing unit, electrically connected to the thermal image capturing device, configured to determine whether the tracer gas is leaking out of the case according to the thermal images of the case.

Abstract: A controlling system for controlling an electronic device equipped in a vehicle. The controlling system includes a touch input device, a control unit and a display device. The touch input device is arranged on a roof of the vehicle and configured to receive inputs. The control unit is electrically connected to the touch input device and configured to control the operations of the electronic device based on the inputs. The electronic device is arranged elsewhere other than the roof of the vehicle. The display device arranged in front of a driver and configured to display at least one control option for the operations of the control unit.

Abstract: In some embodiments, in a method, for each array of at least a first array, a layout of the first array which comprises a plurality of cells, and a plurality of first circuit paths running across at least one side length in an array size configuration of the first array is received. Each of the plurality of cells is configured with a first node that is coupled to a respective one of the plurality of first circuit paths. A first representative characteristic associated with the plurality of first circuit paths is extracted. A universal cell model applied to each cell in a second array is generated based on a base cell model comprising parameters independent of positions in the second array, and the first representative characteristic.

Abstract: A driving assistance system includes a first camera disposed in the vehicle and configured to capture a visible image; a second camera disposed in the vehicle and configured to capture an invisible image; a display device configured to display images to the driver; and a processor coupled to the first camera, the second camera, and the display device, the processor conducts a process of image fusion to combine the visible image and the invisible image to obtain a fused image; wherein the display device displays the fused image only when the clarity of the visible image falls below a preset threshold.

Abstract: A driving assistance system includes a database configured to store numbers of preset criteria concerning various driving conditions, a sensor, configured to sense environmental data surrounding a vehicle; a thermal image capturing device, configured to capture a thermal images surrounding the vehicle; a display device; and a processor, coupled to the sensor, the thermal image capturing device and the display device. The processor compares the environmental data against the preset criteria to determine the driving condition of the vehicle. The display device automatically display thermal images to inform and provide precautions to the driver if the driving condition indicates that the driver's vision is adversely affected.

Abstract: A driving intention indicating device includes a projection system and a control unit. The projection system is arranged on a vehicle. The control unit is configured to control the projection system according to a change in a gear position of a gearbox of the vehicle. When the gear position of the gearbox of the vehicle is switched from a first gear position to a second gear position, the control unit is configured to control the projection system to project an indicating image on a road surface close the vehicle according to a moving direction of the second gear position, in order to indicate a moving direction of the vehicle from a parked position.

Abstract: A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N?1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.

Abstract: A method comprises receiving, in a computer, an input indicative of a drawing of at least a portion of at least one layer of a semiconductor device. The at least one portion of the at least one layer is compared to corresponding portions in corresponding layers of a plurality of previously defined devices stored in a non-transitory machine readable storage medium. Each layer of at least one of the plurality of previously defined devices for which the corresponding portion in the corresponding layer matches the at least one portion of the at least one layer of the semiconductor device is displayed on a display device.

Abstract: One or more systems and techniques for modeling are provided. An original device model, such as a SPICE model, is used as a basis for fabricating a semiconductor arrangement, such as an integrated circuit arrangement, upon a semiconductor wafer. Fabrication process variations cause measured e-parameters and measured size e-parameters of the semiconductor arrangement to vary from original design parameters of the original device model. Accordingly, a partial set of e-parameters and a partial set of size e-parameters are measured from the semiconductor arrangement, and are expanded into a full set of e-parameters and a full set of size e-parameters using e-parameter derivation and size-centric derivation. The original device model is retargeted using the full set of e-parameters and the full set of size e-parameters to create a new device model that more accurately represents the real-world or fabricated semiconductor arrangement.

Abstract: The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width.

Abstract: In some embodiments, a circuit comprises a plurality of memory banks, a column line tracking loop and/or a row line tracking loop, and a tracking circuit. The plurality of memory banks are arranged in a plurality of rows and a plurality of columns of memory building blocks. The column line tracking loop traverses at least a portion of the plurality of rows. The row line tracking loop traverses at least a portion of the plurality of columns. The tracking circuit is configured to receive a first edge of a first signal, cause the first edge of a first signal to be propagated through the column line tracking loop and/or through the row line tracking loop and cause a second edge of the first signal when receiving the propagated first edge of the first signal. The first signal is associated with accessing of the plurality of memory banks.

Abstract: A method of determining a device type and device properties includes receiving an input file including information related to a device, and identifying at least one layer set within the input file. The method further includes identifying at least one feature present in layer set. The method further includes analyzing a relationship between the at least one feature formed by the first layer and at least one feature formed by the second layer to determine at least one layer set relationship. The method further includes comparing the layer set relationship with at least one template layer set relationship. The method further includes determining the device type of the device based on the comparison between the layer set relationship and the template layer set relationship. The method further includes determining the device properties of the device based on the layer set relationship, the device type or the at least one feature.

Abstract: In some embodiments, a circuit comprises a plurality of memory banks, a column line tracking loop and/or a row line tracking loop, and a tracking circuit. The plurality of memory banks are arranged in a plurality of rows and a plurality of columns of memory building blocks. The column line tracking loop traverses at least a portion of the plurality of rows. The row line tracking loop traverses at least a portion of the plurality of columns. The tracking circuit is configured to receive a first edge of a first signal, cause the first edge of a first signal to be propagated through the column line tracking loop and/or through the row line tracking loop and cause a second edge of the first signal when receiving the propagated first edge of the first signal. The first signal is associated with accessing of the plurality of memory banks.

Abstract: A semiconductor device design method includes generating a layout of a semiconductor device based on schematic data. The layout includes location data for at least one electrical component. The method includes receiving first voltage data associated with at least one electrical component. The method includes receiving second voltage data based on simulation results for the semiconductor device. The method includes incorporating, based on the location data of the at least one electrical component, the first voltage data or the second voltage data in the layout to generate a modified layout. The first voltage data or the second voltage data being incorporated in at least one marker layer of the modified layout. The method includes performing a voltage-dependent design rule check (VDRC) on the modified layout. The VDRC analyzes spacing rules associated with the at least one electrical component based on the first voltage data or the second voltage data.

Abstract: In some embodiments, a time division multiplexing (TDM) circuit is configured to receive an external clock signal and generate an internal clock signal that has at least one pulse during a clock cycle of the external clock signal. An address selector is configured to select a current address before a first time within one of the at least one pulse, and select a next address starting from the first time to generate a selected address. An address storage element is configured to receive the selected address from the address selector and provide a passed through or stored address. The provided address is the current address substantially throughout the one of the at least one pulse. A single-port (SP) memory is configured to access at least one SP memory cell at the address provided by the address storage element in response to the internal clock signal.

Abstract: In some embodiments, in a method, for each array of at least a first array, a layout of the first array which comprises a plurality of cells, and a plurality of first circuit paths running across at least one side length in an array size configuration of the first array is received. Each of the plurality of cells is configured with a first node that is coupled to a respective one of the plurality of first circuit paths. A first representative characteristic associated with the plurality of first circuit paths is extracted. A universal cell model applied to each cell in a second array is generated based on a base cell model comprising parameters independent of positions in the second array, and the first representative characteristic.

Abstract: A system and method for tracing a net includes comparing an IC design against a marked portion of the IC design, and extracting a traced net that includes the marked portion from the IC design file. The method also includes displaying the traced net and storing at least one indicator along with information identifying the traced net.

Abstract: A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N?1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.