Abstract: A semiconductor device design method includes generating a layout of a semiconductor device based on schematic data. The layout includes location data for at least one electrical component. The method includes receiving first voltage data associated with at least one electrical component. The method includes receiving second voltage data based on simulation results for the semiconductor device. The method includes incorporating, based on the location data of the at least one electrical component, the first voltage data or the second voltage data in the layout to generate a modified layout. The first voltage data or the second voltage data being incorporated in at least one marker layer of the modified layout. The method includes performing a voltage-dependent design rule check (VDRC) on the modified layout. The VDRC analyzes spacing rules associated with the at least one electrical component based on the first voltage data or the second voltage data.

Abstract: A system and method of designing a semiconductor device comprising loading a design rule manual (DRM) and a design rule check (DRC) into an electronic design tool, wherein the DRM comprises one or more design rules and the DRC comprises one or more design rule checks. Each design rule check is both associated with a corresponding design rule and configured to verify compliance with the corresponding design rule. The method further includes receiving a relevant information, wherein the relevant information comprises a layer number or a selected feature of the semiconductor device, creating, by a processor, a condensed DRM from the DRM, a condensed DRC from the DRC and displaying at least the condensed DRM or condensed DRC by a user interface. The condensed DRM is a portion of the DRM and the condensed DRC is a portion of the DRC.

Abstract: In some embodiments, a time division multiplexing (TDM) circuit is configured to receive an external clock signal and generate an internal clock signal that has at least one pulse during a clock cycle of the external clock signal. An address selector is configured to select a current address before a first time within one of the at least one pulse, and select a next address starting from the first time to generate a selected address. An address storage element is configured to receive the selected address from the address selector and provide a passed through or stored address. The provided address is the current address substantially throughout the one of the at least one pulse. A single-port (SP) memory is configured to access at least one SP memory cell at the address provided by the address storage element in response to the internal clock signal.

Abstract: A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N?1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.

Abstract: A semiconductor device design method includes extracting voltage data associated with at least one electrical component in a layout of a semiconductor device and based on a result of a simulation of an operation of the semiconductor device. Based on location data of the at least one electrical component, the extracted voltage data is incorporated in the layout to generate a modified layout of the semiconductor device. One or more operations of the method are performed by at least one processor.

Abstract: One or more systems and techniques for modeling are provided. An original device model, such as a SPICE model, is used as a basis for fabricating a semiconductor arrangement, such as an integrated circuit arrangement, upon a semiconductor wafer. Fabrication process variations cause measured e-parameters and measured size e-parameters of the semiconductor arrangement to vary from original design parameters of the original device model. Accordingly, a partial set of e-parameters and a partial set of size e-parameters are measured from the semiconductor arrangement, and are expanded into a full set of e-parameters and a full set of size e-parameters using e-parameter derivation and size-centric derivation. The original device model is retargeted using the full set of e-parameters and the full set of size e-parameters to create a new device model that more accurately represents the real-world or fabricated semiconductor arrangement.

Abstract: A method comprises receiving, in a computer, an input indicative of a drawing of at least a portion of at least one layer of a semiconductor device. The at least one portion of the at least one layer is compared to corresponding portions in corresponding layers of a plurality of previously defined devices stored in a non-transitory machine readable storage medium. Each layer of at least one of the plurality of previously defined devices for which the corresponding portion in the corresponding layer matches the at least one portion of the at least one layer of the semiconductor device is displayed on a display device.

Abstract: A design system for designing an integrated circuit, and the design system includes a processor and a computer readable medium embodying computer program code. The computer program code includes instructions executable by the processor and configured to cause the processor to: modify a circuit design of the integrated circuit to compensate for an impact of layout parameters of the circuit design; generate at least one recommended layout parameter of an integrated circuit device within the integrated circuit; calculate a circuit performance parameter of the integrated circuit using the at least one recommended layout parameter; and generate a layout design of the modified circuit design of the integrated circuit according to the at least one recommended layout parameter.

Abstract: A boost system for dual-port SRAM includes a comparator and a boost circuit. The comparator is configured to compare a first row address of a first port and a second row address of a second port, and output a first enable signal. The boost circuit is configured to boost a voltage difference between a first voltage source and a second voltage source according to the first enable signal.

Abstract: A system and method for tracing a net includes comparing an IC design against a marked portion of the IC design, and extracting a traced net that includes the marked portion from the IC design file. The method also includes displaying the traced net and storing at least one indicator along with information identifying the traced net.

Abstract: A method of determining a device type and device properties includes receiving an input file including information related to a device, and identifying at least one layer set within the input file. The method further includes identifying at least one feature present in layer set. The method further includes analyzing a relationship between the at least one feature formed by the first layer and at least one feature formed by the second layer to determine at least one layer set relationship. The method further includes comparing the layer set relationship with at least one template layer set relationship. The method further includes determining the device type of the device based on the comparison between the layer set relationship and the template layer set relationship. The method further includes determining the device properties of the device based on the layer set relationship, the device type or the at least one feature.

Abstract: A boost system for dual-port SRAM includes a comparator and a boost circuit. The comparator is configured to compare a first row address of a first port and a second row address of a second port, and output a first enable signal. The boost circuit is configured to boost a voltage difference between a first voltage source and a second voltage source according to the first enable signal.

Abstract: A system and method of designing a semiconductor device comprising loading a design rule manual (DRM) and a design rule check (DRC) into an electronic design tool, wherein the DRM comprises one or more design rules and the DRC comprises one or more design rule checks. Each design rule check is both associated with a corresponding design rule and configured to verify compliance with the corresponding design rule. The method further includes receiving a relevant information, wherein the relevant information comprises a layer number or a selected feature of the semiconductor device, creating, by a processor, a condensed DRM from the DRM, a condensed DRC from the DRC and displaying at least the condensed DRM or condensed DRC by a user interface. The condensed DRM is a portion of the DRM and the condensed DRC is a portion of the DRC.

Abstract: The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width.

Abstract: A semiconductor device design method includes extracting voltage data associated with at least one electrical component in a layout of a semiconductor device and based on a result of a simulation of an operation of the semiconductor device. Based on location data of the at least one electrical component, the extracted voltage data is incorporated in the layout to generate a modified layout of the semiconductor device. One or more operations of the method are performed by at least one processor.

Abstract: The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width.

Abstract: In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least one processor. Voltage data associated with the at least one electrical component and based on a simulation of an operation of the semiconductor device is extracted by the at least one processor. Based on the extracted location data, the extracted voltage data is incorporated, by the at least one processor, in the layout to generate a modified layout of the semiconductor device.

Abstract: A design system for designing an integrated circuit, and the design system includes a processor and a computer readable medium embodying computer program code. The computer program code includes instructions executable by the processor and configured to cause the processor to: modify a circuit design of the integrated circuit to compensate for an impact of layout parameters of the circuit design; generate at least one recommended layout parameter of an integrated circuit device within the integrated circuit; calculate a circuit performance parameter of the integrated circuit using the at least one recommended layout parameter; and generate a layout design of the modified circuit design of the integrated circuit according to the at least one recommended layout parameter.

Abstract: A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N?1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.

Abstract: A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.