Abstract: A design system for designing an integrated circuit that includes a processor, a memory coupled to the processor, and instructions to generate and edit a schematic of the integrated circuit, generate at least one recommended layout parameter of an integrated circuit device within the integrated circuit, extract the at least one recommended layout parameter during a layout stage of the integrated circuit, and calculate a circuit performance parameter of the integrated circuit using the at least one recommended layout parameter, and a user interface configured to display at least one of the circuit performance parameter and layout constraints of the integrated circuit device of the integrated circuit.

Abstract: The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width.

Abstract: A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N?1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.

Abstract: A design system includes a layout module and a user interface. The layout module includes a computing unit, which is configured to extract layout parameters of an integrated circuit device in a circuit during a layout stage of the circuit, and calculate circuit parameters of the device using the layout parameters. The user interface is configured to display the circuit parameters of the device in response to a user selection of the device.

Abstract: A design system for designing an integrated circuit that includes a processor, a memory coupled to the processor, and instructions to generate and edit a schematic of the integrated circuit, generate at least one recommended layout parameter of an integrated circuit device within the integrated circuit, extract the at least one recommended layout parameter during a layout stage of the integrated circuit, and calculate a circuit performance parameter of the integrated circuit using the at least one recommended layout parameter, and a user interface configured to display at least one of the circuit performance parameter and layout constraints of the integrated circuit device of the integrated circuit.

Abstract: In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least one processor. Voltage data associated with the at least one electrical component and based on a simulation of an operation of the semiconductor device is extracted by the at least one processor. Based on the extracted location data, the extracted voltage data is incorporated, by the at least one processor, in the layout to generate a modified layout of the semiconductor device.

Abstract: A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N?1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.

Abstract: A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.

Abstract: A design system includes a layout module and a user interface. The layout module includes a computing unit, which is configured to extract layout parameters of an integrated circuit device in a circuit during a layout stage of the circuit, and calculate circuit parameters of the device using the layout parameters. The user interface is configured to display the circuit parameters of the device in response to a user selection of the device.

Abstract: A voltage controlled oscillator includes at least one input port for receiving a control voltage and at least one voltage-to-current coupled to the input port for generating a control current in response to the control voltage. At least one current controlled oscillator generates an oscillating frequency output in response to the control current. At least one compensation branch is coupled to the voltage-to-current converter for generating a compensation current that increases the control current when the control voltage exceeds a predetermined value.

Abstract: A method for designing a phase-lock loop (PLL) circuit is disclosed. The method includes the following steps. A first set of intellectual properties, each of which represents a control circuit implemented on a semiconductor substrate, is provided. A second set of intellectual properties, each of which represents a filter implemented on the semiconductor substrate, is provided. Intellectual properties are selected from the first and second sets based on a predetermined specification of the PLL circuit. The selected intellectual properties are integrated as an integrated intellectual property representing the PLL circuit, such that a layout area of the PLL circuit implemented by using the integrated intellectual property is configured based on the predetermined specification.

Abstract: A voltage controlled oscillator includes at least one input port for receiving a control voltage and at least one voltage-to-current coupled to the input port for generating a control current in response to the control voltage. At least one current controlled oscillator generates an oscillating frequency output in response to the control current. At least one compensation branch is coupled to the voltage-to-current converter for generating a compensation current that increases the control current when the control voltage exceeds a predetermined value.

Abstract: A method for designing a phase-lock loop (PLL) circuit is disclosed. The method includes the following steps. A first set of intellectual properties, each of which represents a control circuit implemented on a semiconductor substrate, is provided. A second set of intellectual properties, each of which represents a filter implemented on the semiconductor substrate, is provided. Intellectual properties are selected from the first and second sets based on a predetermined specification of the PLL circuit. The selected intellectual properties are integrated as an integrated intellectual property representing the PLL circuit, such that a layout area of the PLL circuit implemented by using the integrated intellectual property is configured based on the predetermined specification.

Abstract: A method and circuit to produce an optimal sampling phase for recovery of a digital signal is achieved. A digital signal is over-sampled by sampling on each phase of a multiple phase clock to generate a sample value per phase. The multiple phase clock may be generated by a DLL. A voted value is determined per phase comprising a majority value of a set of consecutive sample values. Transition phases are sensed. A transition phase is defined as two consecutive voted phases comprising different values. The transition phases are compared to a stored phase state to determine a signal shift direction. The signal shift direction is filtered to generate a state update signal. The stored phase state is updated based on the state update signal. The stored phase state corresponds to an optimal sampling phase for recovery of the digital signal.

Abstract: A method for analyzing a cell definition comprises the steps of: identifying at least one connectivity target in at least one cell definitions identifying at least one circuit path in the at least one cell definition, the at least one circuit path containing or connected to a circuit portion containing the at least one connectivity target of the cell definition; predicting a routing path to be used by a router to connect a connectivity target in the at least one cell definition to another structure; and determining whether a combination of the predicted routing path and the circuit path causes a violation of an integrated circuit design rule.

Abstract: A method for analyzing a cell definition comprises the steps of: identifying at least one connectivity target in at least one cell definitions identifying at least one circuit path in the at least one cell definition, the at least one circuit path containing or connected to a circuit portion containing the at least one connectivity target of the cell definition; predicting a routing path to be used by a router to connect a connectivity target in the at least one cell definition to another structure; and determining whether a combination of the predicted routing path and the circuit path causes a violation of an integrated circuit design rule.