Abstract: Various implementations described herein are related to a device having bitline drivers coupled to passgates of bitcells via bitlines and buried metal lines formed within a substrate including a buried enable signal line and a buried ground line coupled to ground connections of the bitline drivers. The buried enable signal line transfers a negative bias to a selected bitline of the bitlines via the buried ground line that is coupled to the ground connections of the bitline drivers so as to increase gate-source bias of the passgates of the selected bitcell to thereby enhance write capability of the selected bitcell.

Abstract: Briefly, embodiments, such as methods and/or systems for operations and/or procedures to test magnetic memory devices. In a particular implementation, a bit error rate of a magnetic memory device may be estimated based, at least in part, on an observed bit error rate in the presence of an externally applied magnetic field.

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.

Abstract: Various implementations described herein refer to a method for tracking abnormal incidents while monitoring activity of logic circuitry. The method may include detecting a tamper event related to the abnormal incidents and storing an attack signature related to the tamper event. The attack signature may be stored in non-volatile memory (NVM), such as, e.g., correlated electron random access memory (CeRAM).

Abstract: Various implementations described herein refer to a device having a memory structure with a substrate. The device may have a signal wire buried or partially buried within at least one of the substrate and a dielectric for transmitting electrical signals. The device may be manufactured as a memory device having a memory cell structure with the signal wire buried or partially buried in the substrate.

Abstract: According to one implementation of the present disclosure, a circuit comprises: a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines; and one or more canary circuits coupled to the memory array, wherein each of the canary circuits is configured to predict at least partial breakdown of a corresponding grouping of bitcells in the memory array. According to one implementation of the present disclosure, a method includes: providing an excitation stress on one or more canary circuits corresponding to a grouping of bitcells in a memory array; detecting at least a partial breakdown of the one or more canary circuits; and generating a flag.

Abstract: Various implementations described herein are directed to a device having neural network circuitry with an array of synapse cells arranged in columns and rows. The device may have input circuitry that provides voltage to the synapse cells by way of row input lines for the rows in the array. The device may have output circuitry that receives current from the synapse cells by way of column output lines for the columns in the array. Also, conductance for the synapse cells in the array may be determined based on the voltage provided by the input circuitry and the current received by the output circuitry.

Abstract: Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.

Abstract: According to one implementation of the present disclosure, a method includes fabricating a memory macro unit; forming a through silicon via (TSV); and bonding the TSV at least partially through the fabricated memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

Abstract: Various implementations described herein are directed to a device having a multi-tiered memory structure with a first tier and a second tier arranged vertically in a stacked configuration. The device may have multiple transistors disposed in the multi-tiered memory structure with first transistors disposed in the first tier and second transistors disposed in the second tier. The device may have a single interconnect that vertically couples the first transistors in the first tier to the second transistors in the second tier.

Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

Abstract: According to one implementation of the present disclosure, an integrated circuit comprises a memory macro unit that includes an input/output (I/O) circuit block, where read/write circuitry of the I/O circuit block is apportioned on at least first and second tiers of the memory macro unit. In a particular implementation, read circuitry of the read/write circuitry is arranged on the first tier and write circuitry of the read/write circuitry is arranged on the second tier.

Abstract: A memory for an artificial neural network (ANN) accelerator is provided. The memory includes a first bank, a second bank and a bank selector. Each bank includes at least two word lines and a plurality of read word selectors. Each word line stores a plurality of words, and each word has a plurality of bytes. Each read word selector has a plurality of input ports and an output port, is coupled to a corresponding word in each word line, and is configured to select a byte of the corresponding word of a selected word line based on a byte select signal. The bank selector is coupled to the read word selectors of the first bank and the second bank, and configured to select a combination of read word selectors from at least one of the first bank and the second bank based on a bank select signal.

Abstract: According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.

Abstract: An integrated circuit includes a primary memory array with cells switchable between first and second states. The circuit also includes sacrificial memory cells; each fabricated to be switchable between the first and second states and associated with at least one row of the primary array. A controller is configured to detect a write operation to a row of the primary array, stress a sacrificial cell associated with the row and detect a failure of the associated sacrificial cell. The sacrificial cells are fabricated to have lower write-cycle endurance than cells of the primary array or are subjected to more stress. Failure of a row of the primary array is predicted based, at least in part, on a detected failure of the associated sacrificial cell.

Abstract: A system-on-chip is provided that includes functional circuitry that performs a function. Control circuitry controls the function based one or more configuration parameters. Non-volatile storage circuitry includes a plurality of non-volatile storage cells each being adapted to write at least a bit of the one or more configuration parameters in a rewritable, persistent manner a plurality of times. Read circuitry locally accesses the non-volatile storage circuitry, obtains the one or more configuration parameters from the non-volatile storage circuitry and provides the one or more configuration parameters to the control circuitry. Write circuitry obtains the one or more configuration parameters and provides the one or more configuration parameters to the non-volatile storage circuitry by locally accessing the non-volatile storage circuitry.

Abstract: A compute-in-memory (CIM) array module and a method for performing dynamic saturation detection for a CIM array are provided. The CIM array module includes a CIM array, saturation detection units (SDUs) and a controller. The CIM array includes selectable row signal lines, column signal lines and cells. Each cell is located at an intersection of a selectable row signal line and a column signal line, and each cell has a programmable conductance. The SDUs are selectively coupled to at least one column signal line, and each SDU is configured to, for each column signal line, generate an analog signal, and identify the column signal line as a saturated column signal line when a voltage of the analog signal is greater than a saturation threshold voltage, or a current of the analog signal is greater than a saturation threshold current.

Abstract: Various implementations described herein are directed to a device having a multi-tiered memory structure with a first tier and a second tier arranged vertically in a stacked configuration. The device may have multiple transistors disposed in the multi-tiered memory structure with first transistors disposed in the first tier and second transistors disposed in the second tier. The device may have a single interconnect that vertically couples the first transistors in the first tier to the second transistors in the second tier.

Abstract: A three-dimensional (3D) storage circuit includes two or more tiers of semiconductor dies, and a storage array of bitcells distributed on the two or more tiers to form a plurality of storage subarrays. One of the storage subarrays is arranged on a respective one of the tiers. Row and column replica/dummy tracking cells are arranged on each of the tiers. A timing circuit is coupled to the tracking cells of each of the tiers. In response to receipt of tier-specific trim bits for each of the tiers, the timing circuit independently controls a timing and/or voltage state of each of the tiers during an access operation of the 3D storage circuit to account for process and/or thermal variation between tiers of the 3D storage circuit.

Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline. The integrated circuit may include a write driver coupled to the bitline for writing data to the bitcell. The write driver may have an inverter and a clamping device that are arranged to clamp current after data has been written to the bitcell.