Patents by Inventor Muhammad Khellah

Muhammad Khellah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9805790
    Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Nathaniel J. August, Pulkit Jain, Stefan Rusu, Fatih Hamzaoglu, Rangharajan Venkatesan, Muhammad Khellah, Charles Augustine, Carlos Tokunaga, James W. Tschanz, Yih Wang
  • Patent number: 9685208
    Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkarni, Anupama Thaploo, Iqbal Rajwani, Kyung-Hoae Koo, Eric A. Karl, Muhammad Khellah
  • Publication number: 20160232968
    Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.
    Type: Application
    Filed: December 5, 2013
    Publication date: August 11, 2016
    Applicant: Intel Corporation
    Inventors: Nathaniel J. AUGUST, Pulkit JAIN, Stefan RUSU, Fatih HAMZAOGLU, Rangharajan VENKATESAN, Muhammad KHELLAH, Charles AUGUSTINE, Carlos TOKUNAGA, James W. TSCHANZ, Yih WANG
  • Publication number: 20160225419
    Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.
    Type: Application
    Filed: April 8, 2016
    Publication date: August 4, 2016
    Inventors: Jaydeep P. Kulkarni, Anupama Thaploo, Iqbal Rajwani, Kyung-Hoae Koo, Eric A. Karl, Muhammad Khellah
  • Patent number: 9355694
    Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 31, 2016
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkarni, Anupama Thaploo, Iqbal Rajwani, Kyung-Hoae Koo, Eric A. Karl, Muhammad Khellah
  • Publication number: 20150279438
    Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Inventors: Jaydeep P. Kulkarni, Anupama Thaploo, Iqbal Rajwani, Kyung-Hoae Koo, Eric A. Karl, Muhammad Khellah
  • Patent number: 8769376
    Abstract: Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: July 1, 2014
    Assignee: Intel Corporation
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Nam Sung Kim, Vivek De
  • Patent number: 8667367
    Abstract: Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: March 4, 2014
    Assignee: Intel Corporation
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Nam Sung Kim, Vivek De
  • Patent number: 8462541
    Abstract: A register file employing a shared supply structure to improve the minimum supply voltage.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: June 11, 2013
    Assignee: Intel Corporation
    Inventors: Vivek De, DiaaEldin S. Khalil, Muhammad Khellah, Moty Mehalel, George Shchupak
  • Patent number: 8456923
    Abstract: Provided herein is a new RF implementation. Instead of using a pre-charged High node for one or more of its evaluation nodes, it employs an evaluation (or evaluate) node that is discharged (Low) prior to evaluation and enters evaluation in a discharged state. In some embodiments, with such “normally Low” evaluation nodes, it uses pull-up stack devices, rather than pull-down devices, to charge the evaluate node during an evaluate phase if the logic so dictates.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: June 4, 2013
    Assignee: Intel Corporation
    Inventors: Bibiche Geuskens, Ataur Patwary, Eric Kwesi Donkoh, Muhammad Khellah, Tanay Karnik
  • Publication number: 20130024752
    Abstract: Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.
    Type: Application
    Filed: September 25, 2012
    Publication date: January 24, 2013
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Nam Sung Kim, Vivek De
  • Patent number: 8245111
    Abstract: A processor may comprise a cache, which may be divided into a first and second section while the processor operates in a low-power mode. A cache line of the first section may be fragmented into segments. A first encoder may generate first data bits and check bits while encoding a first portion of a data stream and a second encoder may, separately, generate second data bits and check bits while encoding a second portion of the data stream. The first data bits may be stored in a first segment of the first section and the check bits in a first portion of the second section that is associated with the first segment. The first decoder may correct errors in multiple bit positions within the first data bits using the check bits stored in the first portion and the second decoder may, separately, decode the second data bits using the second set of check bits.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: August 14, 2012
    Assignee: Intel Corporation
    Inventors: Zeshan A. Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Dinesh Somasekhar, Muhammad Khellah, Shih-Lien Lu
  • Publication number: 20120110266
    Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
    Type: Application
    Filed: December 31, 2011
    Publication date: May 3, 2012
    Inventors: Christopher Wilkerson, M. Muhammad Khellah, Vivek De, Ming Y. Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
  • Publication number: 20120106285
    Abstract: A register file employing a shared supply structure to improve the minimum supply voltage.
    Type: Application
    Filed: January 10, 2012
    Publication date: May 3, 2012
    Inventors: Vivek De, DiaaEldin S. Khalil, Muhammad Khellah, Moty Mehalel, George Shchupak
  • Patent number: 8111579
    Abstract: A register file employing a shared supply structure to improve the minimum supply voltage.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: February 7, 2012
    Assignee: Intel Corporation
    Inventors: Vivek De, DiaaEldin S. Khalil, Muhammad Khellah, Moty Mehalel, George Shchupak
  • Publication number: 20100157705
    Abstract: Provided herein is a new RF implementation. Instead of using a pre-charged High node for one or more of its evaluation nodes, it employs an evaluation (or evaluate) node that is discharged (Low) prior to evaluation and enters evaluation in a discharged state. In some embodiments, with such “normally Low” evaluation nodes, it uses pull-up stack devices, rather than pull-down devices, to charge the evaluate node during an evaluate phase if the logic so dictates.
    Type: Application
    Filed: December 18, 2008
    Publication date: June 24, 2010
    Inventors: Bibiche Geuskens, Ataur Patwary, Eric Kwesi Donkoh, Muhammad Khellah, Tanay Karnik
  • Publication number: 20100146368
    Abstract: A processor may comprise a cache, which may be divided into a first and second section while the processor operates in a low-power mode. A cache line of the first section may be fragmented into segments. A first encoder may generate first data bits and check bits while encoding a first portion of a data stream and a second encoder may, separately, generate second data bits and check bits while encoding a second portion of the data stream. The first data bits may be stored in a first segment of the first section and the check bits in a first portion of the second section that is associated with the first segment. The first decoder may correct errors in multiple bit positions within the first data bits using the check bits stored in the first portion and the second decoder may, separately, decode the second data bits using the second set of check bits.
    Type: Application
    Filed: December 9, 2008
    Publication date: June 10, 2010
    Inventors: Zeshan A. Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Dinesh Somasekhar, Muhammad Khellah, Shih-Lien Lu
  • Publication number: 20080162986
    Abstract: For one disclosed embodiment, an apparatus may comprise a memory cell to store a bit value, wherein the memory cell may lose the bit value in response to a memory access operation. The apparatus may also comprise first circuitry to detect whether the memory cell loses the bit value in response to the memory access operation and second circuitry to restore the bit value in the memory cell in response to detection that the memory cell loses the bit value. Other embodiments are also disclosed.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventors: Nam Sung Kim, Muhammad Khellah, Yibin Ye, Dinesh Somasekhar, Vivek De
  • Publication number: 20070076463
    Abstract: According to embodiments of the present invention, a one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. In on embodiment, access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De
  • Publication number: 20070058419
    Abstract: For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 15, 2007
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Nam Kim, Yibin Ye, Vivek De, Kevin Zhang, Bo Zheng