Patents by Inventor Muhammad Khellah

Muhammad Khellah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070002607
    Abstract: In some embodiments, a memory array is provided comprising columns of SRAM bit cells, the columns each comprising a bit line and a sense amplifier coupled to the bit line, the sense amplifier to maintain a state in a selected cell of its bit line during a read operation. Other embodiments are disclosed herein.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Vivek De
  • Publication number: 20070002611
    Abstract: A cell in an information storage cell array is written, by asserting a signal on a bit line that is coupled to the cell and to a group of other cells in the array, to a first voltage. The cell is read by asserting a signal on a word line that is coupled to the cell and to another group of cells in the array, in a direction of, but without reaching, the first voltage. Other embodiments are also described and claimed.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Yibin Ye, Muhammad Khellah, Dinesh Somasekhar, Ali Keshavarzi, Fabrice Paillet, Vivek De
  • Publication number: 20070004162
    Abstract: A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used to generate the MIM capacitor is adaptable to current logic processing techniques. Other embodiments are described and claimed.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
  • Publication number: 20060291265
    Abstract: A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.
    Type: Application
    Filed: June 27, 2005
    Publication date: December 28, 2006
    Inventors: Gerhard Schrom, Fabrice Paillet, Tanay Karnik, Dinesh Somasekhar, Yibin Ye, Ali Keshavarzi, Muhammad Khellah, Vivek De
  • Publication number: 20060285393
    Abstract: A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.
    Type: Application
    Filed: June 21, 2005
    Publication date: December 21, 2006
    Inventors: Fabrice Paillet, Ali Keshavarzi, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De, Tanay Karnik
  • Publication number: 20060279985
    Abstract: In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of memory cells. A plurality of bit lines are interconnected to columns of memory cells. Driving signals provided via the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.
    Type: Application
    Filed: June 14, 2005
    Publication date: December 14, 2006
    Inventors: Ali Keshavarzi, Stephen Tang, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Vivek De, Gerhard Schrom
  • Publication number: 20060268626
    Abstract: In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: May 25, 2005
    Publication date: November 30, 2006
    Inventors: Fatih Hamzaoglu, Kevin Zhang, Nam Kim, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Vivek De, Bo Zheng
  • Publication number: 20060267093
    Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.
    Type: Application
    Filed: May 4, 2006
    Publication date: November 30, 2006
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Brian Doyle, Suman Datta, Vivek De
  • Publication number: 20060262610
    Abstract: A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors.
    Type: Application
    Filed: May 23, 2005
    Publication date: November 23, 2006
    Applicant: Intel Corporation
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Vivek De, James Tschanz, Stephen Tang
  • Publication number: 20060187706
    Abstract: A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.
    Type: Application
    Filed: February 22, 2005
    Publication date: August 24, 2006
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
  • Publication number: 20060184595
    Abstract: In general, in one aspect, the disclosure describes an apparatus inluding a representative majority voter gate to analyze bit transitions of a pluraility of bits. The plurailuty of bits are analzed in groups. The representative majority voter gate generates an invert signal based on the analysis. The apparatus further inludes a conditional inverter to apply the invert signal to the pluraility of bits.
    Type: Application
    Filed: February 16, 2005
    Publication date: August 17, 2006
    Inventors: James Tschanz, Mircea Stan, Muhammad Khellah, Yibin Ye, Vivek De
  • Publication number: 20060139995
    Abstract: A one time programmable memory includes isolated gate transistors that may be programmed by subjecting the isolated gate transistors to voltage conditions that degrade characteristics of the isolated gate transistors. The degraded characteristics may be sensed to read the memory.
    Type: Application
    Filed: December 28, 2004
    Publication date: June 29, 2006
    Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De
  • Publication number: 20060114711
    Abstract: In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line.
    Type: Application
    Filed: December 1, 2004
    Publication date: June 1, 2006
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Gunjan Pandya, Vivek De
  • Publication number: 20060109028
    Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
    Type: Application
    Filed: December 22, 2005
    Publication date: May 25, 2006
    Inventors: Maged Ghoneima, Peter Caputa, Muhammad Khellah, Ram Krishnamurthy, James Tschanz, Yibin Ye, Vivek De, Yehia Ismail
  • Publication number: 20060104128
    Abstract: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.
    Type: Application
    Filed: December 30, 2005
    Publication date: May 18, 2006
    Inventors: Dinesh Somasekhar, Muhammad Khellah, Yibin Ye, Vivek De, James Tschanz, Stephen Tang
  • Publication number: 20060098482
    Abstract: Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.
    Type: Application
    Filed: November 30, 2005
    Publication date: May 11, 2006
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
  • Publication number: 20060092742
    Abstract: Different embodiments of a one-time-programmable antifuse cell are provided in this disclosure. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.
    Type: Application
    Filed: November 1, 2004
    Publication date: May 4, 2006
    Inventors: Fabrice Paillet, Ali Keshavarzi, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De
  • Patent number: 7031203
    Abstract: A DRAM memory cell uses a single transistor to perform the data storage and switching functions of a conventional cell. The transistor has a floating channel body which stores a potential that corresponds to one of two digital data values. The transistor further includes a gate connected to a first word line, a drain connected to a second word line, and a source connected to a bit line. By setting the word and bit lines to specific voltage states, the channel body stores a digital one potential as a result of impact ionization and a digital zero value as a result of forward bias of body-to-source junction.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: April 18, 2006
    Assignee: Intel Corporation
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Vivek De
  • Publication number: 20060071646
    Abstract: A method is described that induced dielectric breakdown within a capacitor's dielectric material while driving a current through the capacitor. The current is specific to data that is being written into the capacitor. The method also involves reading the data by interpreting behavior of the capacitor that is determined by the capacitor's resistance, where, the capacitor's resistance is a consequence of the inducing and the driving.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 6, 2006
    Inventors: Fabrice Paillet, Ali Keshavarzi, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Alavi Mohsen, Vivek De
  • Publication number: 20060067133
    Abstract: A method and apparatus for a one-phase write to a one-transistor memory cell array. In one embodiment, the method includes a one-phase write to a selected wordline of a memory cell array. Once the wordline is selected, a logical zero value is stored within at least one memory cell of the selected wordline of the memory cell array. Simultaneously, a logical 0 value is stored within at least one memory cell of the selected wordline of the selected memory cell array. Other embodiments are described and claimed.
    Type: Application
    Filed: September 30, 2004
    Publication date: March 30, 2006
    Inventors: Yibin Ye, Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Gerhard Schrom, Vivek De