Patents by Inventor Muhammad Khellah

Muhammad Khellah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050135169
    Abstract: An apparatus and method for generating a reference in a memory circuit are disclosed. At least two dummy bit-cells are used to generate a reference voltage. One cell has high value stored and the other has a low value stored. The cells are activated and discharged into respective bit-lines. The bit-lines are equalized during the discharge process to generate a reference that is approximately a mid point between a high value cell and a low value cell.
    Type: Application
    Filed: December 22, 2003
    Publication date: June 23, 2005
    Inventors: Dinesh Somasekhar, Yibin Ye, Muhammad Khellah, Fabrice Paillet, Stephen Tang, Ali Keshavarzi, Shih-Lien Lu, Vivek De
  • Patent number: 6903984
    Abstract: A DRAM memory cell uses a single transistor to perform the data storage and switching functions of a conventional cell. The transistor has a floating channel body which stores a potential that corresponds to one of two digital data values. The transistor further includes a gate connected to a first word line, a drain connected to a second word line, and a source connected to a bit line. By setting the word and bit lines to specific voltage states, the channel body stores a digital one potential as a result of impact ionization and a digital zero value as a result of forward bias of body-to-source junction.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: June 7, 2005
    Assignee: Intel Corporation
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Vivek De
  • Publication number: 20050111255
    Abstract: Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.
    Type: Application
    Filed: November 26, 2003
    Publication date: May 26, 2005
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
  • Publication number: 20050105342
    Abstract: A row of floating-body single transistor memory cells is written to in two phases.
    Type: Application
    Filed: November 19, 2003
    Publication date: May 19, 2005
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
  • Patent number: 6724648
    Abstract: A power management device and static random access memory (SRAM) architecture with dynamic supply voltages reduce active power leakage in SRAM cells. When a cell is inactive, a low level supply voltage is applied to the source line connected to the cell to maintain the data stored in the cell. However, before a cell is accessed (e.g., during a read or write operation), the source line is raised to a high level supply voltage.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: April 20, 2004
    Assignee: Intel Corporation
    Inventors: Muhammad Khellah, Vivek De, Dinesh Somasekhar, Yibin Ye
  • Publication number: 20030189849
    Abstract: A power management device and static random access memory (SRAM) architecture with dynamic supply voltages reduce active power leakage in SRAM cells. When a cell is inactive, a low level supply voltage is applied to the source line connected to the cell to maintain the data stored in the cell. However, before a cell is accessed (e.g., during a read or write operation), the source line is raised to a high level supply voltage.
    Type: Application
    Filed: April 5, 2002
    Publication date: October 9, 2003
    Inventors: Muhammad Khellah, Vivek De, Dinesh Somasekhar, Yibin Ye