Patents by Inventor Muhammad Khellah

Muhammad Khellah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060067109
    Abstract: A method is described that comprises modulating the power consumption of an SRAM as a function of its usage at least by reaching, with help of a transistor, a voltage on a node within an operational amplifier's feedback loop. The voltage is beyond another voltage that the operational amplifier would drive the node to be without the help of the transistor. The voltage helps the feedback loop establish a voltage drop across a cell within the SRAM.
    Type: Application
    Filed: September 30, 2004
    Publication date: March 30, 2006
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, James Tschanz, Stephen Tang, Vivek De
  • Publication number: 20060067126
    Abstract: A system to write to a plurality of memory cells coupled to a word line, each of the plurality of memory cells comprising a transistor having a source, a drain, a body and a gate coupled to the word line. Some embodiments provide biasing of one or more of the plurality of memory cells in saturation to inject charge carriers into the body of the one or more of the plurality of memory cells, and biasing of each of the plurality of memory cells in accumulation to tunnel charge carriers from the body of each of the plurality of memory cells to the gate of each of the plurality of memory cells.
    Type: Application
    Filed: September 30, 2004
    Publication date: March 30, 2006
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
  • Publication number: 20060067152
    Abstract: Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 30, 2006
    Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De
  • Publication number: 20060061382
    Abstract: Apparatus and systems, as well as methods and articles, may operate to provide a majority voter indication using a sense amplifier coupled to a first plurality of bit inputs and to a second plurality of bit inputs.
    Type: Application
    Filed: September 23, 2004
    Publication date: March 23, 2006
    Inventors: Yibin Ye, James Tschanz, Muhammad Khellah, Vivek De
  • Publication number: 20060054933
    Abstract: Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.
    Type: Application
    Filed: November 7, 2005
    Publication date: March 16, 2006
    Inventors: Ali Keshavarzi, Stephen Tang, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
  • Publication number: 20060054971
    Abstract: Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.
    Type: Application
    Filed: November 7, 2005
    Publication date: March 16, 2006
    Inventors: Ali Keshavarzi, Stephen Tang, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
  • Publication number: 20060054977
    Abstract: A memory device is provided that includes a plurality of memory cells where each memory cell includes a source region, a drain region and a floating gate. A coupling bit-line is also provided that extends over at least one column of the plurality of memory cells. The coupling bit-line may be formed on each of the floating gates of memory cells forming the column of the plurality of memory cells. The coupling bit-line may also be formed within a well of each of memory cells forming the column of the plurality of memory cells.
    Type: Application
    Filed: September 16, 2004
    Publication date: March 16, 2006
    Inventors: Dinesh Somasekhar, Shekhar Borkar, Vivek De, Yibin Ye, Muhammad Khellah, Fabrice Paillet, Stephen Tang, Ali Keshavarzi, Shih-Lien Lu
  • Publication number: 20060014331
    Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 19, 2006
    Applicant: Intel Corporation
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Brian Doyle, Suman Datta, Vivek De
  • Publication number: 20060001103
    Abstract: A device includes an interconnect structure having a number of circuit paths to transfer signals. The circuit paths transfer the signals at different speed to reduce the coupling capacitance effect between adjacent circuit paths.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Maged Ghoneima, Muhammad Khellah, James Tschanz, Yibin Ye, Vivek De
  • Publication number: 20060002211
    Abstract: A two transistor memory cell includes a write transistor and a read transistor. When reading the memory cell, the read transistor is turned on, and a voltage develops on a read bit line.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Yibin Ye, Dinesh Somasekhar, Muhammad Khellah, Fabrice Paillet, Stephen Tang, Ali Keshavarzi, Shih-Lien Lu, Vivek De
  • Publication number: 20050285616
    Abstract: A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 29, 2005
    Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De
  • Publication number: 20050226032
    Abstract: A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inverter configuration so as to apply a forward body bias to the PMOS transistors of the cross-coupled inverter configuration. A power control unit may control a supply voltage to each of the PMOS transistors as well as apply the switching signal to the NMOS transistor based on a STANDBY mode of the memory cell.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 13, 2005
    Inventors: Stephen Tang, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Vivek De, James Tschanz
  • Publication number: 20050225459
    Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 13, 2005
    Inventors: Maged Ghoneima, Peter Caputa, Muhammad Khellah, Ram Krishnamurthy, James Tschanz, Yibin Ye, Vivek De, Yehea Ismail
  • Publication number: 20050213370
    Abstract: A SRAM memory cell comprising cross-coupled inverters, each cross-coupled inverter comprising a pull-up transistor, where the pull-up transistors are forward body biased during read operations. Forward body biasing improves the read stability of the memory cell. Other embodiments are described and claimed.
    Type: Application
    Filed: March 26, 2004
    Publication date: September 29, 2005
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Ali Farhang, Gunjan Pandya, Vivek De
  • Publication number: 20050146956
    Abstract: Some embodiments provide pre-charge of a bit-line coupled to a memory cell to a reference voltage using a pre-charge device, discharge of the bit-line based on a value stored by the memory cell, injection during the discharge, of a first current into the bit-line using the pre-charge device, and injection, during the discharge, of a second current into a reference bit-line using a second pre-charge device. Also during the discharge, a difference is sensed between a voltage on the bit-line and a voltage on the reference bit-line.
    Type: Application
    Filed: December 24, 2003
    Publication date: July 7, 2005
    Inventors: Dinesh Somasekhar, Yibin Ye, Muhammad Khellah, Fabrice Paillet, Stephen Tang, Ali Keshavarzi, Shih-Lien Lu, Vivek De
  • Publication number: 20050145935
    Abstract: Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.
    Type: Application
    Filed: December 31, 2003
    Publication date: July 7, 2005
    Inventors: Ali Keshavarzi, Stephen Tang, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
  • Publication number: 20050145886
    Abstract: Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.
    Type: Application
    Filed: December 31, 2003
    Publication date: July 7, 2005
    Inventors: Ali Keshavarzi, Stephen Tang, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
  • Publication number: 20050146921
    Abstract: A two-transistor DRAM cell includes an NMOS device and a PMOS device coupled to the NMOS device.
    Type: Application
    Filed: December 30, 2003
    Publication date: July 7, 2005
    Inventors: Yibin Ye, Dinesh Somasekhar, Muhammad Khellah, Fabrice Paillet, Stephen Tang, Ali Keshavarzi, Shih-Lien Lu, Vivek De
  • Publication number: 20050141290
    Abstract: A DRAM memory cell uses a single transistor to perform the data storage and switching functions of a conventional cell. The transistor has a floating channel body which stores a potential that corresponds to one of two digital data values. The transistor further includes a gate connected to a first word line, a drain connected to a second word line, and a source connected to a bit line. By setting the word and bit lines to specific voltage states, the channel body stores a digital one potential as a result of impact ionization and a digital zero value as a result of forward bias of body-to-source junction.
    Type: Application
    Filed: February 28, 2005
    Publication date: June 30, 2005
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Vivek De
  • Publication number: 20050135162
    Abstract: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.
    Type: Application
    Filed: December 18, 2003
    Publication date: June 23, 2005
    Inventors: Dinesh Somasekhar, Muhammad Khellah, Yibin Ye, Vivek De, James Tschanz, Stephen Tang