Abstract: A Metal Oxide Semiconductor (MOS) cell design has traditional planar cells extending in a first dimension, and trenches with their length extending in a third dimension, orthogonal to the first dimension in a top view. The manufacturing process includes forming a horizontal channel, and a plurality of trenches discontinued in the planar cell regions. Horizontal planar channels are formed in the mesa of the orthogonal trenches. A series connected horizontal planar channel and a vertical trench channel are formed along the trench regions surrounded by the first base. The lack of a traditional vertical channel is important to avoid significant reliability issues (shifts in threshold voltage Vth). The planar cell design offers a range of advantages both in terms of performance and processability. Manufacture of the planar cell is based on a self-aligned process with minimum number of masks, with the potential of applying additional layers or structures.

Abstract: A Metal Oxide Semiconductor (MOS) trench cell concept adopts on a first surface of a semiconductor body a plurality of main gates extending lengthwise parallel to one another, and forming MOS channels, with transistor cell regions formed in a mesa of the semiconductor body between neighbouring main gates, and a drift layer in the semiconductor body s. The power semiconductor includes a plurality of second gates interwoven with the main gates at an angle of 45 degrees to 90 degrees to the longitudinal direction of the main gates. An additional gate structure can also be added to interconnect the second gates, leading to additional design flexibility by enabling forming additional MOS channels in the power semiconductor. The new design can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials such as Silicon Carbide SiC or Gallium Nitride GaN.

Abstract: A Metal Oxide Semiconductor (MOS) transistor cell design has a source region and a first base layer extending in a third dimension. When a control voltage greater than a threshold value is applied on the gate trench, electrons flow from a singular point within the source region, into a radial MOS channel formed on the lateral walls of those trench regions surrounded by the first base layer, but not abutting on the higher doped second base layer. The MOS channel width is determined by a quadrant centred on the singular point and with a radius equal to the separation region between the singular point and the maximum surface doping concentration point in the first base layer.

Abstract: A Metal Oxide Semiconductor (MOS) cell design has traditional planar cells extending in a first dimension, and trenches with their length extending in a third dimension, orthogonal to the first dimension in a top view. The manufacturing process includes forming a horizontal channel, and a plurality of trenches discontinued in the planar cell regions. Horizontal planar channels are formed in the mesa of the orthogonal trenches. A series connected horizontal planar channel and a vertical trench channel are formed along the trench regions surrounded by the first base. The lack of a traditional vertical channel is important to avoid significant reliability issues (shifts in threshold voltage Vth). The planar cell design offers a range of advantages both in terms of performance and processability. Manufacture of the planar cell is based on a self-aligned process with minimum number of masks, with the potential of applying additional layers or structures.

Abstract: A module arrangement for power semiconductor devices, includes two or more heat spreading layers with a first surface and a second surface being arranged opposite to the first surface. At least two or more power semiconductor devices are arranged on the first surface of the heat spreading layer and electrically connected thereto. An electrical isolation stack comprising an electrically insulating layer and electrically conductive layers is arranged in contact with the second surface of each heat spreading layer. The at least two or more power semiconductor devices, the heat spreading layers and a substantial part of each of the electrical isolation stacks are sealed from their surrounding environment by a molded enclosure. Accordingly, similar or better thermal characteristic of the module can be achieved instead of utilizing high cost electrically insulating layers, and double side cooling configurations can be easily implemented, without the use of a thick baseplate.

Abstract: A MOS cell based on a simple and self-aligned process is provides a planar cell forming a horizontal MOS channel, and a plurality of trench regions, which are arranged at an angle with respect to the longitudinal direction of the planar cells. The new cell concept can adopt both planar MOS channels and Trench MOS channels in a single MOS cell structure, or planar MOS channels alone, while utilising the trenches to improve the current spreading of the planar MOS channels. Floating P-doped regions at the bottom of the trench regions protect the device against high peak electric fields. The orthogonal trench recesses are discontinued in their longitudinal direction to allow the planar channels to conduct electrons. The design can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials.

Abstract: An insulated gate bipolar transistor includes a source electrode, a collector electrode, a source layer, a base layer, a drift layer and a collector layer. Trench gate electrodes extend through the base layer into the drift layer. A channel is located between the source layer, the base layer and the drift layer. A trench Schottky electrode is adjacent to one of the trench gate electrodes and includes an electrically conductive Schottky layer arranged lateral to the base layer and extends through the base layer into the drift layer. The Schottky layer is electrically connected to the source electrode. Collection areas are located in the drift layer at a respective trench gate electrode bottom of the trench gate electrodes or of the trench Schottky electrode. The Schottky layer forms a Schottky contact to the collection area at a contact area.

Abstract: A thin non-punch-through semiconductor device with a patterned collector layer on the collector side is proposed. The thin NPT RC-IGBT semiconductor device has a collector layer with a pattern of p/n shorts, an emitter side structured as a functional MOS cell, a base layer arranged between the emitter and the collector sides, but without the use of a buffer/field-stop layer. A low doped bipolar gain control layer having a thickness of less than 10 ?m may be used in combination with a short pattern of the collector to reduce the bipolar gain and achieve thinner devices with lower losses and high operating temperature capability. The doping concentration of the base layer and a thickness of the base layer are adapted such that the distance from the end of the electric field region to the patterned collector, at breakdown voltage, is less than 15% of the total device thickness.

Abstract: A semiconductor device with an active transistor cell comprising a p-doped first and second base layers, surrounding an n type source region, the device further comprising a plurality of first gate electrodes embedded in trench recesses, has additional fortifying p-doped layers embedding the opposite ends of the trench recesses. The additional fortifying layers do not affect the active cell design in terms of cell pitch i.e., the design rules for transistor cell spacing, or hole drainage between the transistor cells, but reduce the gate-collector parasitic capacitance of the semiconductor, hence leading to optimum low conduction and switching losses. To further reduce the gate-collector capacitance, the trench recesses embedding the first gate electrodes can be formed with thicker insulating layers in regions that do not abut the first base layers, so as not to negatively impact the value of the threshold voltage.

Abstract: A Metal Oxide Semiconductor (MOS) transistor cell design has multiple trench recesses embedding trench gate electrodes longitudinally extending in a third dimension, with interconnected first base layer, source regions, and a second base layer covering portions of the regions between adjacent trench recesses and longitudinally extending in the same third dimension. When a control voltage greater than a threshold value is applied on the trench gate electrodes, no vertical MOS channels are formable on the trench walls because each of trench recesses abuts at least one source regions and a connected highly doped second base layer. Instead, the charge carriers flow from a singular point within the source region, into a radial MOS channel formed only on the lateral walls of those trench regions abutting the first base layer, but not the higher doped second base layer.

Abstract: A hybrid switch for a power converter and a method of operating said hybrid switch, the hybrid switch comprising: at a minimum a first and a second element comprising one or more switching devices of a first semiconductor type, and at a minimum a third element comprising one or more switching devices of a second semiconductor type, wherein the second semiconductor type is different from the first semiconductor type, and wherein each element is independently configurable and connected to a separate respective control terminal; and, a controller connected to the control terminals, wherein the controller is configured to control each element independently through each respective control terminal, and wherein the controller is further configured to activate elements based on a measured or estimated current and/or power as required by an operating condition of the converter.

Abstract: In this patent application, a new Metal Oxide Semiconductor MOS planar cell design concept is proposed. The inventive power semiconductor includes a planar cell forming a horizontal channel and a plurality of trenches, which are arranged orthogonally to the plane of the planar cells. A second p base layer is introduced which extends perpendicularly deeper than the source region and laterally to the same distance/extent as the source region. Therefore, a vertical channel is prevented from forming in the trench regions while allowing the horizontal channels to form. This is extremely important in order to avoid significant issues (i.e. shifts in Vth) encountered in prior art IGBT designs. The new cell concept adopts planar MOS channel and Trench technology in a single MOS cell structure.

Abstract: Power transistors relying on planar MOS cell designs suffer from the “hole drainage effect”; addition of an enhancement layer creates significant loss of breakdown voltage capability. The Fortified Enhanced Planar MOS cell design provides an alternative that uses enhancement layers, field oxides, and gate trenches without suffering from the loss of blocking voltage. A low doped P-type “fortifying layer” reduces the high peak electric fields that develop in blocking mode in critical regions. The fortifying layer can be electrically biased through an additional electrical contact, which can be arranged at die level, not at transistor cell level. Due to the low dopant concentration of the fortifying layer, no additional MOS channels need to be formed, and the electrons will flow thru the non-inverted regions of the fortifying layer. The new design shows advantages in performance, ease of processing, and applicability.

Abstract: A power transistor layout structure is described that includes a planar cell with a planar gate electrode forming an horizontal MOS channel, and a plurality of trench recesses with gate electrodes, which are arranged at various angles to the longitudinal direction of the planar cells. This cell concept can adopt both planar MOS channels, and Trench MOS channels in a single MOS cell structure. As an alternative, the planar cell gate electrode may be grounded. The device is easy to manufacture based on a self-aligned process with minimum number of masks, with the potential of applying additional layers.

Abstract: A semiconductor device with an active transistor cell comprising a p-type first and second base layers, surrounding an n-type source region, the device further comprising a plurality of first gate electrodes embedded in trench recesses, has additional gate runners formed adjacent to the first base layer, outside the active cell, and contacting the first gate electrodes at the cross points thereof. The additional gate runners do not affect the active cell design in terms of cell pitch i.e., the design rules for cell spacing, hole drainage between the cells, or gate-collector capacitance, hence resulting in optimum low conduction and switching losses. The transistor cell and layout designs offer a range of advantages both in terms of performance and manufacturability, with the potential of applying additional layers or structures.

Abstract: A reverse conducting insulated gate power semiconductor device is provided which comprises a plurality of active unit cells (40) and a pilot diode unit cell (50) comprising a second conductivity type anode region (51) in direct contact with a first main electrode (21) and extending from a first main side (11) to a first depth (d1). Each active unit cell (40) comprises a first conductivity type first source layer (41a) in direct contact with the first main electrode (21), a second conductivity type base layer (42) and a first gate electrode (47a), which is separated from the first source layer (41a) and the second conductivity type base layer (42) by a first gate insulating layer (46a) to form a first field effect transistor structure. A lateral size (w) of the anode region (51) in an orthogonal projection onto a vertical plane perpendicular to the first main side (11) is equal to or less than 1 ?m.

Abstract: A bipolar semiconductor device includes at least a four-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact separated from the first main side by at least a base layer of first conductivity type. A shorting layer of the first conductivity type is arranged on the second main side of the base layer. A third layer includes a patterned highly conductive material, such as metal and/or silicides, graphene, etc., and is deposited on the shorting. A fourth layer of the second conductivity type is arranged directly on the third layer, inserted between the shorting layer and the second electrical contact. This concept can be applied to any non-punch-through or punch-through reverse conducting IGBT designs, but is particularly effective for devices using thin wafers, and is also applicable to bipolar diodes in order to improve a soft recovery process.

Abstract: A Metal Oxide Semiconductor (MOS) trench cell includes a plurality of main gate trenches etched in the semiconductor body. In conduction state, the main gate electrode forms vertical MOS channels on the short edges and at least on a portion of the long edges in a mesa of the semiconductor body between neighbouring trenches. The longitudinal direction of the main gate trenches is oriented at an angle between 45 degrees to 90 degrees compared to the longitudinal direction of the first main electrode contacts, in a top plane view. This design offers a wide range of advantages both in terms of performance (reduced losses, improved controllability and reliability) and processability (narrow mesa design rules) and can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials such as silicon carbide SiC, zinc oxide (ZnO), gallium oxide (Ga2O3), gallium nitride (GaN), diamond.

Abstract: An insulated gate power semiconductor device (1a), comprises in an order from a first main side (20) towards a second main side (27) opposite to the first main side (20) a first conductivity type source layer (3), a second conductivity type base layer (4), a first conductivity type enhancement layer (6) and a first conductivity type drift layer (5). The insulated gate power semiconductor device (1a) further comprises two neighbouring trench gate electrodes (7) to form a vertical MOS cell sandwiched between the two neighbouring trench gate electrodes (7). At least a portion of a second conductivity type protection layer (8a) is arranged in an area between the two neighbouring trench gate electrodes (7), wherein the protection layer (8a) is separated from the gate insulating layer (72) by a first conductivity type channel layer (60a; 60b) extending along the gate insulating layer (72).

Abstract: An insulated gate power semiconductor device (1a), comprises in an order from a first main side (20) towards a second main side (27) opposite to the first main side (20) a first conductivity type source layer (3), a second conductivity type base layer (4), a first conductivity type enhancement layer (6) and a first conductivity type drift layer (5). The insulated gate power semiconductor device (1a) further comprises two neighbouring trench gate electrodes (7) to form a vertical MOS cell sandwiched between the two neighbouring trench gate electrodes (7). At least a portion of a second conductivity type protection layer (8a) is arranged in an area between the two neighbouring trench gate electrodes (7), wherein the protection layer (8a) is separated from the gate insulating layer (72) by a first conductivity type channel layer (60a; 60b) extending along the gate insulating layer (72).