Abstract: A power semiconductor device is provided comprising a wafer, wherein in a termination region of the device a passivation layer structure is formed at least on a portion of a surface of the wafer and the passivation layer structure comprises in an order from the surface of the wafer in a direction away from the wafer a semi-insulating layer, a silicon nitride layer, an undoped silicate glass layer and an organic dielectric layer. The silicon nitride layer has a layer thickness of at least 0.5 ?m. The organic dielectric layer its attached to the undoped silicate glass layer and the undoped silicate glass layer is attached to the silicon nitride layer.

Abstract: A solid state switch has at least one FET-type device and at least one thyristor-type device coupled in parallel to the at least one FET-type device. The at least one FET-type device is constructed with a first power loss profile based on a rated current of an electrical device; and the at least one thyristor-type device is constructed with a second power loss profile based on a surge current associated with the electrical device.

Abstract: A semiconductor module comprises reverse conducting IGBT connected in parallel with a wide bandgap MOSFET, wherein each of the reverse conducting IGBT and the wide bandgap MOSFET comprises an internal anti-parallel diode.

Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) for forming two channel layers applying a first mask and applying a p first dopant, for forming two source regions forming a second mask by applying a further layer on the lateral sides of the first mask and applying an n second dopant, for forming two well layers forming a third mask by removing such part of the second mask between the source regions and applying a p third dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers; wherein the well layers surround the plug in the lateral direction and separate it from the two source regions.

Abstract: An IGBT is provided comprising at least two first cells (1, 1?), each of which having an n doped source layer (2), a p doped base layer (3), an n doped enhancement layer (4), wherein the base layer (3) separates the source layer (2) from the enhancement layer (4), an n? doped drift layer (5) and a p doped collector layer (6). Two trench gate electrodes (7, 7?) are arranged on the lateral sides of the first cell (1, 1?). The transistor comprises at least one second cell (15) between the trench gate electrodes (7, 7?) of two neighboured first cells (1, 1?), which has on the emitter side (90) a p+ doped well (8) and a further n doped enhancement layer (40, 40?) which separates the well (8) from the neighboured trench gate electrodes (7, 7?).

Abstract: A semiconductor power rectifier with increased surge current capability is described. A semiconductor layer includes a drift layer having a first conductivity type, at least one pilot region having a second conductivity type different from the first conductivity type, a plurality of stripe-shaped emitter regions having the second conductivity type, and a transition region having the second conductivity type, wherein the at least one pilot region has in any lateral direction parallel to the first main side a width of at least 200 ?m and is formed adjacent to the first main side to form a first p-n junction with the drift layer, each emitter region is formed adjacent to the first main side form a second p-n junction with the drift layer, and the transition region is formed adjacent to the first main side to form a third p-n junction with the drift layer.

Abstract: A wide bandgap semiconductor device is comprising an (n?) doped drift layer between a first main side and a second main side. On the first main side, n doped source regions are arranged which are laterally surrounded by p doped channel layers having a channel layer depth. P+ doped well layers having a well layer depth, which is at least as large as the channel layer depth is arranged at the bottom of the source regions. A p++ doped plug extends from a depth, which is at least as deep as the source layer depth and less deep than the well layer depth, to a plug depth, which is as least as deep as the well layer depth, and having a higher doping concentration than the well layers, is arranged between the source regions and well layers. On the first main side, an ohmic contact contacts as a first main electrode the source regions, the well layers and the plug.

Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) forming source regions by applying a first mask with a first and second mask layer and applying an n dopant, forming a well layer by removing such part of the first mask, which is arranged between the two source regions, and applying a p dopant, forming two channel regions by forming a third mask by performing an etching step, by which the first mask layer is farther removed at the openings than the second mask layer, and then removing the second mask layer, wherein the remaining first mask layer forms a third mask and applying a p dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers.

Abstract: A reverse-conducting MOS device is provided having an active cell region and a termination region. Between a first and second main side. The active cell region comprises a plurality of MOS cells with a base layer of a second conductivity type. On the first main side a bar of the second conductivity type, which has a higher maximum doping concentration than the base layer, is arranged between the active cell region and the termination region, wherein the bar is electrically connected to the first main electrode. On the first main side in the termination region a variable-lateral-doping layer of the second conductivity type is arranged. A protection layer of the second conductivity type is arranged in the variable-lateral-doping layer, which protection layer has a higher maximum doping concentration than the maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer.

Abstract: A power device comprises at least one power semiconductor module comprising a wide bandgap semiconductor element; and a cooling system for actively cooling the wide bandgap semiconductor element with a cooling medium, wherein the cooling system comprises a refrigeration device for lowering a temperature of the cooling medium below an ambient temperature of the power device; wherein the cooling system is adapted for lowering the temperature of the cooling medium in such a way that a temperature of the wide bandgap semiconductor element is below 100° C.

Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) for forming two channel layers applying a first mask and applying a p first dopant, for forming two source regions forming a second mask by applying a further layer on the lateral sides of the first mask and applying an n second dopant, for forming two well layers forming a third mask by removing such part of the second mask between the source regions and applying a p third dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers; wherein the well layers surround the plug in the lateral direction and separate it from the two source regions.

Abstract: A semiconductor module and a stack arrangement of semiconductor modules is proposed. The semiconductor module comprises an insulated gate bipolar transistor, a wide band-gap switch, a base plate, and a press device. The insulated gate bipolar transistor and the wide band-gap switch are connected in parallel and are each mounted with a first planar terminal to a side of the base plate. Further, a second planar terminal of the insulated gate bipolar transistor and a second planar terminal of the wind band-gap switch are connected with an electrically conductive connection element, and the press device is arranged on the second planar terminal of the insulated gate bipolar transistor. Hence, when arranging the semiconductor modules in a stack arrangement, any press force is primarily applied to the insulated gate bipolar transistors of the semiconductor modules.

Abstract: A semiconductor power rectifier with increased surge current capability is described, which has a semiconductor layer having a first main side and a second main side opposite to the first main side. The semiconductor layer includes a drift layer having a first conductivity type, at least one pilot region having a second conductivity type different from the first conductivity type, a plurality of stripe-shaped emitter regions having the second conductivity type, and a transition region having the second conductivity type, wherein the at least one pilot region has in any lateral direction parallel to the first main side a width of at least 200 ?m and is formed adjacent to the first main side to form a first p-n junction with the drift layer, each emitter region is formed adjacent to the first main side form a second p-n junction with the drift layer, and the transition region is formed adjacent to the first main side to form a third p-n junction with the drift layer.

Abstract: A bidirectional power semiconductor device with full turn-off control in both current directions and improved electrical and thermal properties is provided, the device comprises a plurality of first gate commutated thyristor (GCT) cells and a plurality of second GCT cells alternating with each other, a first base layer of each first GCT cell is separated from a neighbouring second anode layer of a neighbouring second GCT cell by a first separation region, and a second base layer of each second GCT cell is separated from a neighbouring first anode layer of a neighbouring first GCT cell by a second separation region.

Abstract: A power semiconductor device is provided comprising a wafer, wherein in a termination region of the device a passivation layer structure is formed at least on a portion of a surface of the wafer and the passivation layer structure comprises in an order from the surface of the wafer in a direction away from the wafer a semi insulating layer, a silicon nitride layer, an undoped silicate glass layer and an organic dielectric layer. The silicon nitride layer has a layer thickness of at least 0.5 ?m. The organic dielectric layer its attached to the undoped silicate glass layer and the undoped silicate glass layer is attached to the silicon nitride layer.

Abstract: A method for manufacturing a wide bandgap junction barrier Schottky diode having an anode side and a cathode side is provided, wherein an (n+) doped cathode layer is arranged on the cathode side, at least on p doped anode layer is arranged on the anode side, an (n?) doped drift layer is arranged between the cathode layer and the at least one anode layer, which drift layer extends to the anode side, wherein the following manufacturing steps are performed: a) providing an (n+) doped wide bandgap substrate, b) creating the drift layer on the cathode layer, c) creating the at least one anode layer on the drift layer, d) applying a first metal layer on the anode side on top of the drift layer for forming a Schottky contact, characterized in, that e) creating a second metal layer on top of at least one anode layer, wherein after having created the first and the second metal layer, a metal layer on top of the at least one anode layer has a second thickness and a metal layer on top of the drift layer has a first thic

Abstract: A solid state switch has at least one FET-type device and at least one thyristor-type device coupled in parallel to the at least one FET-type device. The at least one FET-type device is constructed with a first power loss profile based on a rated current of an electrical device; and the at least one thyristor-type device is constructed with a second power loss profile based on a surge current associated with the electrical device.

Abstract: A solid state switch for connecting and disconnecting an electrical device has at least one FET-type device and at least one thyristor-type device coupled in parallel to the at least one FET-type device. A gate driver is operative to send gate drive signals to the at least one FET-type device and to the at least one thyristor-type device for providing current to the electrical device. The gate driver is constructed to control a split of the current as between the at least one FET-type device and the at least one thyristor-type device.

Abstract: A termination region of an IGBT is described, in which surface p-rings are combined with oxide/polysilicon-filled trenches, buried p-rings and surface field plates, so as to obtain an improved distribution of potential field lines in the termination region. The combination of surface ring termination and deep ring termination offers a significant reduction in the amount silicon area which is required for the termination region.

Abstract: A power device comprises at least one power semiconductor module comprising a wide bandgap semiconductor element; and a cooling system for actively cooling the wide bandgap semiconductor element with a cooling medium, wherein the cooling system comprises a refrigeration device for lowering a temperature of the cooling medium below an ambient temperature of the power device; wherein the cooling system is adapted for lowering the temperature of the cooling medium in such a way that a temperature of the wide bandgap semiconductor element is below 100° C.