Abstract: Power transistors relying on planar MOS cell designs suffer from the “hole drainage effect”; addition of an enhancement layer creates significant loss of breakdown voltage capability. The Fortified Enhanced Planar MOS cell design provides an alternative that uses enhancement layers, field oxides, and gate trenches without suffering from the loss of blocking voltage. A low doped P-type “fortifying layer” reduces the high peak electric fields that develop in blocking mode in critical regions. The fortifying layer can be electrically biased through an additional electrical contact, which can be arranged at die level, not at transistor cell level. Due to the low dopant concentration of the fortifying layer, no additional MOS channels need to be formed, and the electrons will flow thru the non-inverted regions of the fortifying layer. The new design shows advantages in performance, ease of processing, and applicability.

Abstract: A power transistor layout structure is described that includes a planar cell with a planar gate electrode forming an horizontal MOS channel, and a plurality of trench recesses with gate electrodes, which are arranged at various angles to the longitudinal direction of the planar cells. This cell concept can adopt both planar MOS channels, and Trench MOS channels in a single MOS cell structure. As an alternative, the planar cell gate electrode may be grounded. The device is easy to manufacture based on a self-aligned process with minimum number of masks, with the potential of applying additional layers.

Abstract: A bidirectional thyristor device includes a semiconductor wafer with a number of layers forming pn junctions. A first main electrode and a first gate electrode are arranged on a first main side of the wafer. A second main electrode and a second gate electrode are arranged on a second main side of the wafer. First emitter shorts penetrate through a first semiconductor layer and second emitter shorts penetrate through a fifth semiconductor layer. In an orthogonal projection onto a plane parallel to the first main side, a first area occupied by the first semiconductor layer and the first emitter shorts overlaps in an overlapping area with a second area occupied by the fifth semiconductor layer and the second emitter shorts. The overlapping area, in which the first area overlaps with the second area, encompasses at least 50% of a total wafer area occupied by the semiconductor wafer.

Abstract: A power semiconductor device includes a Si chip providing a Si switch and a wide bandgap material chip providing a wide bandgap material switch, wherein the Si switch and the wide bandgap material switch are electrically connected in parallel. A method for controlling a power semiconductor device includes: during a normal operation mode, controlling at least the wide bandgap material switch for switching a current through the power semiconductor device by applying corresponding gate signals to at least the wide bandgap material switch; sensing a failure in the power semiconductor device; and, in the case of a sensed failure, controlling the Si switch by applying a gate signal, such that a current is generated in the Si chip heating the Si chip to a temperature forming a permanent conducting path through the Si chip.

Abstract: A MOS cell based on a simple and self-aligned process is provides a planar cell forming a horizontal MOS channel, and a plurality of trench regions, which are arranged at an angle with respect to the longitudinal direction of the planar cells. The new cell concept can adopt both planar MOS channels and Trench MOS channels in a single MOS cell structure, or planar MOS channels alone, while utilising the trenches to improve the current spreading of the planar MOS channels. Floating P-doped regions at the bottom of the trench regions protect the device against high peak electric fields. The orthogonal trench recesses are discontinued in their longitudinal direction to allow the planar channels to conduct electrons. The design can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials.

Abstract: A semiconductor module comprises reverse conducting IGBT connected in parallel with a wide bandgap MOSFET, wherein each of the reverse conducting IGBT and the wide bandgap MOSFET comprises an internal anti-parallel diode. A method for operating a semiconductor module with the method including the steps of: determining a reverse conduction start time, in which the semiconductor module starts to conduct a current in a reverse direction, which reverse direction is a conducting direction of the internal anti-parallel diodes; applying a positive gate signal to the wide bandgap MOSFET after the reverse conduction start time; determining a reverse conduction end time based on the reverse conduction start time, in which the semiconductor module ends to conduct a current in the reverse direction; and applying a reduced gate signal to the wide bandgap MOSFET a blanking time interval before the reverse conduction end time, the reduced gate signal being adapted for switching the wide bandgap MOSFET into a blocking state.

Abstract: An Enhanced Planar MOS cell based on a simple and self-aligned process provides a structure where the lateral distance between the edge of the gate electrode opening and the end of the P-well region is less than 70% from the vertical distance between the surface of the substrate and the depth of the P-well region. Usually, for previous designs, this ratio was 70-80% or more. A spacer can be introduced at the edge of the polysilicon gate electrode openings after the diffusion of an enhancement layer. Using the spacer, a P-type implant is made, resulting in a shorter lateral MOS channel, while the vertical depth of the P-well remains unchanged. The design results in much lower on-state losses without affecting the voltage blocking capability of the device. This design offers advantages both in terms of performance and processability and can be applied to both IGBTs and MOSFETs.

Abstract: A Metal Oxide Semiconductor (MOS) trench cell includes a plurality of main gate trenches etched in the semiconductor body. In conduction state, the main gate electrode forms vertical MOS channels on the short edges and at least on a portion of the long edges in a mesa of the semiconductor body between neighbouring trenches. The longitudinal direction of the main gate trenches is oriented at an angle between 45 degrees to 90 degrees compared to the longitudinal direction of the first main electrode contacts, in a top plane view. This design offers a wide range of advantages both in terms of performance (reduced losses, improved controllability and reliability) and processability (narrow mesa design rules) and can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials such as silicon carbide SiC, zinc oxide (ZnO), gallium oxide (Ga2O3), gallium nitride (GaN), diamond.

Abstract: A bipolar semiconductor device includes at least a four-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact separated from the first main side by at least a base layer of first conductivity type. A shorting layer of the first conductivity type is arranged on the second main side of the base layer. A third layer includes a patterned highly conductive material, such as metal and/or silicides, graphene, etc., and is deposited on the shorting. A fourth layer of the second conductivity type is arranged directly on the third layer, inserted between the shorting layer and the second electrical contact. This concept can be applied to any non-punch-through or punch-through reverse conducting IGBT designs, but is particularly effective for devices using thin wafers, and is also applicable to bipolar diodes in order to improve a soft recovery process.

Abstract: A Metal Oxide Semiconductor (MOS) cell design has traditional planar cells extending in a first dimension, and trenches with their length extending in a third dimension, orthogonal to the first dimension in a top view. The manufacturing process includes forming a horizontal channel, and a plurality of trenches discontinued in the planar cell regions. Horizontal planar channels are formed in the mesa of the orthogonal trenches. A series connected horizontal planar channel and a vertical trench channel are formed along the trench regions surrounded by the first base. The lack of a traditional vertical channel is important to avoid significant reliability issues (shifts in threshold voltage Vth). The planar cell design offers a range of advantages both in terms of performance and processability. Manufacture of the planar cell is based on a self-aligned process with minimum number of masks, with the potential of applying additional layers or structures.

Abstract: A bidirectional thyristor device includes a semiconductor wafer with a number of layers forming pn junctions. A first main electrode and a first gate electrode are arranged on a first main side of the wafer. A second main electrode and a second gate electrode are arranged on a second main side of the wafer. First emitter shorts penetrate through a first semiconductor layer and second emitter shorts penetrate through a fifth semiconductor layer. In an orthogonal projection onto a plane parallel to the first main side, a first area occupied by the first semiconductor layer and the first emitter shorts overlaps in an overlapping area with a second area occupied by the fifth semiconductor layer and the second emitter shorts. The overlapping area, in which the first area overlaps with the second area, encompasses at least 50% of a total wafer area occupied by the semiconductor wafer.

Abstract: A power semiconductor device includes a base plate; a Si chip including a Si substrate, the Si chip attached to the base plate; a first metal preform pressed with a first press pin against the Si chip; a wide bandgap material chip comprising a wide bandgap substrate and a semiconductor switch provided in the wide bandgap substrate, the wide bandgap material chip attached to the base plate; and a second metal preform pressed with a second press pin against the wide bandgap material chip; the Si chip and the wide bandgap material chip are connected in parallel via the base plate and via the first press pin and the second press pin; the first metal preform is adapted for forming a conducting path through the Si chip, when heated by an overcurrent; and the second metal preform is adapted for forming an temporary conducting path through the wide bandgap material chip or an open circuit, when heated by an overcurrent.

Abstract: A thin non-punch-through semiconductor device with a patterned collector layer on the collector side is proposed. The thin NPT RC-IGBT semiconductor device has a collector layer with a pattern of p/n shorts, an emitter side structured as a functional MOS cell, a base layer arranged between the emitter and the collector sides, but without the use of a buffer/field-stop layer. A low doped bipolar gain control layer having a thickness of less than 10 ?m may be used in combination with a short pattern of the collector to reduce the bipolar gain and achieve thinner devices with lower losses and high operating temperature capability. The doping concentration of the base layer and a thickness of the base layer are adapted such that the distance from the end of the electric field region to the patterned collector, at breakdown voltage, is less than 15% of the total device thickness.

Abstract: An IGBT is provided with at least two first cells, each of which have an n doped source layer, a p doped base layer, an n doped enhancement layer. The base layer separates the source layer from the enhancement layer, an n-doped drift layer and a p doped collector layer. Two trench gate electrodes are arranged on the lateral sides of the first cell. The transistor includes at least one second cell between the trench gate electrodes of two neighboring first cells, which has on the emitter side a p+ doped well and a further n doped enhancement layer which separates the well from the neighboring trench gate electrodes. An insulator layer stack is arranged on top of the second cell on the emitter side to insulate the second cell and the neighboring trench gate electrodes from the metal emitter electrode.

Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) forming source regions by applying a first mask with a first and second mask layer and applying an n dopant, forming a well layer by removing such part of the first mask, which is arranged between the two source regions, and applying a p dopant, forming two channel regions by forming a third mask by performing an etching step, by which the first mask layer is farther removed at the openings than the second mask layer, and then removing the second mask layer, wherein the remaining first mask layer forms a third mask and applying a p dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers.

Abstract: A solid state switch for connecting and disconnecting an electrical device has at least one FET-type device and at least one thyristor-type device coupled in parallel to the at least one FET-type device. A gate driver is operative to send gate drive signals to the at least one FET-type device and to the at least one thyristor-type device for providing current to the electrical device. The gate driver is constructed to control a split of the current as between the at least one FET-type device and the at least one thyristor-type device.

Abstract: A wide bandgap semiconductor device is comprising an (n?) doped drift layer between a first main side and a second main side. On the first main side, n doped source regions are arranged which are laterally surrounded by p doped channel layers having a channel layer depth. P+ doped well layers having a well layer depth, which is at least as large as the channel layer depth is arranged at the bottom of the source regions. A p++ doped plug extends from a depth, which is at least as deep as the source layer depth and less deep than the well layer depth, to a plug depth, which is as least as deep as the well layer depth, and having a higher doping concentration than the well layers, is arranged between the source regions and well layers. On the first main side, an ohmic contact contacts as a first main electrode the source regions, the well layers and the plug.

Abstract: A power semiconductor device includes a Si chip providing a Si switch and a wide bandgap material chip providing a wide bandgap material switch, wherein the Si switch and the wide bandgap material switch are electrically connected in parallel. A method for controlling a power semiconductor device includes: during a normal operation mode, controlling at least the wide bandgap material switch for switching a current through the power semiconductor device by applying corresponding gate signals to at least the wide bandgap material switch; sensing a failure in the power semiconductor device; and, in the case of a sensed failure, controlling the Si switch by applying a gate signal, such that a current is generated in the Si chip heating the Si chip to a temperature forming a permanent conducting path through the Si chip.

Abstract: A power semiconductor device includes a base plate; a Si chip including a Si substrate, the Si chip attached to the base plate; a first metal preform pressed with a first press pin against the Si chip; a wide bandgap material chip comprising a wide bandgap substrate and a semiconductor switch provided in the wide bandgap substrate, the wide bandgap material chip attached to the base plate; and a second metal preform pressed with a second press pin against the wide bandgap material chip; the Si chip and the wide bandgap material chip are connected in parallel via the base plate and via the first press pin and the second press pin; the first metal preform is adapted for forming a conducting path through the Si chip, when heated by an overcurrent; and the second metal preform is adapted for forming an temporary conducting path through the wide bandgap material chip or an open circuit, when heated by an overcurrent.

Abstract: A power semiconductor device is provided comprising a wafer, wherein in a termination region of the device a passivation layer structure is formed at least on a portion of a surface of the wafer and the passivation layer structure comprises in an order from the surface of the wafer in a direction away from the wafer a semi-insulating layer, a silicon nitride layer, an undoped silicate glass layer and an organic dielectric layer. The silicon nitride layer has a layer thickness of at least 0.5 ?m. The organic dielectric layer its attached to the undoped silicate glass layer and the undoped silicate glass layer is attached to the silicon nitride layer.