Abstract: Systems, methods, and devices are disclosed for front-lit displays having uniform brightness. In one embodiment, an example display may include an electrophoretic display, a light guide configured to direct light from one or more light emitting diodes, and a cover lens assembly. The cover lens assembly may include a cover glass layer, an anti-glare film coupled to the cover glass layer, and a hot melt adhesive disposed about lateral edge surfaces of the cover glass layer and the anti-glare film, such that the hot melt adhesive forms a perimeter of the cover lens assembly.

Abstract: A motor drive system includes a MUX circuit, a DC voltage scaling circuit, a fault detection circuit, an ADC, and an FPGA. The MUX circuit selectively establishes a MUX input signal path and a MUX output signal path. The DC voltage scaling circuit measures a DC link voltage. The fault detection circuit receives the output DC link voltage and outputs one of a normal operation signal or a fault signal in response to comparing the DC link voltage to one or both of a U/V reference voltage and an O/V reference voltage. The ADC converts one or more input analog voltages into respective corresponding output digital voltages. The FPGA is in signal communication with the ADC output (ADCOUT) and the MUX circuit, and is configured to control the motor drive system based on a comparison between one or more of the output digital voltages.

Abstract: A switch control system includes a first voltage source configured to output a first source voltage on a first voltage line. The system includes a first gate driver, a second gate driver, a third gate driver, and a fourth gate driver. Each of the gate drivers includes shoot through protection (STP) configured to prevent a first switch and a second switch of the system from ever both being closed at once thereby preventing shoot voltages from a DC bus to ground through the first and second switches.

Abstract: Disclosed are systems, apparatuses, processes, and computer-readable media to capture images with subjects at different depths of fields. For instance, a method of processing image data includes obtaining a first image captured using an image sensor with a first exposure. The method may further include obtaining a second image captured using the image sensor with a second exposure. The method may include compressing the second image based on a comparison of the second image with the first image and storing the compressed second image in a memory. The method may further include obtaining the compressed second image from the memory and decompressing the compressed second image based on a difference between the compressed second image and the first image. The method may further include generating a combined image at least in part by combining the first image and the second image.

Abstract: A process for the preparation of (R)-4-propyl-pyrrolidine-2-one, is provided which includes enzymatic conversion of dimethyl 3-propyl pentanedioate selectively into (S)-3-(2-methoxy-2-oxoethyl) hexanoic acid using Novozyme's Promea® enzyme, amidation of (S)-3-(2-methoxy-2-oxoethyl) hexanoic acid, followed by ester hydrolysis to obtain (S)-3-(2-amino-2-oxoethyl) hexanoic acid having high chiral purity >99% and converting the amide to amine by Hofmann rearrangement and cyclization resulting in (R)-4-propyl-pyrrolidine-2-one. It is further converted to Brivaracetam by N-alkylation with 2-bromobutyric acid, esterification followed by enzymatic resolution.

Abstract: A process for the preparation of (R)-4-propyl-pyrrolidine-2-one, is provided which includes enzymatic conversion of dimethyl 3-propyl pentanedioate selectively into (S)-3-(2-methoxy-2-oxoethyl) hexanoic acid using Novozyme's Promea® enzyme, amidation of (S)-3-(2-methoxy-2-oxoethyl) hexanoic acid, followed by ester hydrolysis to obtain (S)-3-(2-amino-2-oxoethyl) hexanoic acid having high chiral purity>99% and converting the amide to amine by Hofmann rearrangement and cyclization resulting in (R)-4-propyl-pyrrolidine-2-one. It is further converted to Brivaracetam by N-alkylation with 2-bromobutyric acid, esterification followed by enzymatic resolution.

Abstract: A resistance temperature detector includes a single channel analog to digital converter (ADC) comprising a first channel input and a reference voltage input. The detector also includes a resistance temperature detector (RTD) element connected to the first channel input and a current sense element in series with the RTD element. The current sense element is connected to the reference voltage input. The detector also includes a power source connected to the RTD element and a controller configured to: receive an output of the single channel ADC to determine a temperature at the RTD element. The output of the single channel ADC comprises a bit representation of a ratio between a first voltage across the RTD element and a reference voltage across the current sense element.

Abstract: A switch control system can include a voltage source configured to output a source voltage on a voltage line, and a first gate driver connected to a gate control signal line to receive a gate control signal from a controller. The first gate driver can be connected to the voltage line to receive the source voltage, and the first gate driver can be connected to a first terminal line to output a first gate voltage signal to a first terminal of a switch. The system can include an inverter connected to the gate control signal line configured to receive the gate control signal and output an inverted gate control signal. The system can include a second gate driver connected to the inverter to receive the inverted gate control signal from the inverter. The second gate driver can be connected to the voltage line to receive the source voltage, and the second gate driver can be connected to a second terminal line to output a second gate voltage signal to a second terminal of a switch.

Abstract: A circuit calibration system can include a calibration voltage source, a calibration output line, and a variable voltage system connected between the calibration voltage source and the calibration output line. The variable voltage system can be configured to provide a variable calibration voltage to the calibration output line.

Abstract: An intelligent architecture system is provided. The intelligent architecture system includes an input line, an output line and an intelligent architecture operably interposed between the input line and the output line. The intelligent architecture is configured to control a voltage of the output line in accordance with a voltage of the input line.

Abstract: A system and method for testing a resolver circuit is provided. Aspects include a resolver circuit including an excitation signal output, a sine signal input, and a cosine signal input, a switching matrix comprising an excitation input connected to the excitation signal output, a first output connected to the sine signal input, and a second output connected to the cosine signal input, wherein the switching matrix further includes a set of switches configured to route an excitation signal from the resolver circuit to mimic a sine and cosine signal output corresponding to a specified angle for a resolver sensor, a controller configured to operate the resolver circuit to output an excitation signal, determine an angle value based on a sine signal received and a cosine signal received from the switching matrix, and compare the angle value to the specified angle to determine a fault condition in the resolver circuit.

Abstract: A voltage measurement system and method is provided. Aspects include a comparator having a positive and a negative input terminal, a processor configured to supply a reference voltage signal to the negative input terminal, wherein the positive input terminal receives an input voltage, setting the reference voltage signal to a zero voltage signal, determine a line frequency of the input voltage based on a timing signal from the comparator and determining a first pulse width of the input signal based on the timing signal, set the reference voltage to a PWM signal with a fixed duty cycle, receive the timing signal from the output of the comparator, determine a rising edge and a falling edge associated with the input voltage based on the timing signal, and determine a peak value of the input voltage based on a second pulse width between the rising and falling edge.

Abstract: System and methods for accuracy improvement of an LVDT are provided. Aspects include determining a first voltage from the first PGA and a second voltage from the second PGA, wherein the first voltage is determined from a PGA coupled to a first secondary winding, and wherein the second voltage is determined from a second PGA coupled to a second secondary winding, iteratively performing: analyzing the first voltage to determine a gain correction is needed for a first gain for the first PGA, the gain correction comprising change to the first gain, and analyzing the second voltage to determine a gain correction is needed for a second gain for the second PGA, the gain correction comprising change to the second gain, based on determining a gain correction is not needed for the first gain and the second gain, calculating a position based on the first voltage and the second voltage.

Abstract: Systems and techniques are described herein for processing frames. For example, a process can include obtaining a current frame from a sequence of frames, the current frame associated with a first bit depth resolution and a reference frame preceding the current frame associated with the first bit depth and resolution. The process can include determining a difference between a first pixel value of the current frame and a second pixel value of the reference frame, the first pixel value and the second pixel value associated with a corresponding first pixel position. The process can include outputting a first portion of the determined difference as a first output value and, based on a determination that the determined difference does not exceed a maximum magnitude of a second bit depth, outputting an indication that the determined difference does not include a second portion associated with the first pixel position.

Abstract: A motor drive system includes a direct current (DC) bus that provides a DC link voltage across a DC link capacitor, and a split DC link mid-point circuit connected in parallel with the DC link capacitor. The split DC link mid-point circuit establishes a mid-point reference based on the DC link voltage. A power inverter is in signal communication with the DC bus. The power inverter includes one or more gate driver units configured to drive one or more corresponding switches. Each gate driver unit includes a mid-point ground connection that is connected to the mid-point reference. The split DC link mid-point circuit can define a voltage divide that establishes the mid-point reference and can be used to monitor the DC link voltage.

Abstract: Protecting data in non-volatile storages provided to clouds against malicious attacks. According to an aspect, multiple malicious patterns indicating respective malicious attacks to access non-volatile storages provided to clouds in a cloud infrastructure are maintained. When an access request is received, the data stream representing the access request is examined to determine whether the data stream contains any of the malicious patterns. If the data stream is found not to contain any malicious pattern, it is concluded that the access request is free of the malicious attacks. If the data stream is found to contain at least one malicious pattern, it is concluded that the access request is a malicious attack corresponding to the malicious pattern.

Abstract: A threshold detection system can be configured to monitor a location (e.g., a DC link) for overcurrent. The threshold detection system can be configured to generate a pulse width modulated signal with a duty cycle that is proportional to current through the DC link. The threshold detection system can be configured to determine whether the duty cycle exceeds a selected threshold.

Abstract: One or more embodiments relates to a system for simultaneously detecting vibration and the presence of a target gas having a tunable fiber ring laser in electronic and optical communication with a vibration sensor and a gas detection sensor. One or more embodiments relate to a method for simultaneously measuring vibration and detecting the presence of a target gas in an environment having the steps of providing a system for simultaneously measuring vibration and detecting a target gas into an environment; sending an optical signal to a vibration sensor and gas detection sensor; and collecting and analyzing modified signals from the vibration sensor and gas detection sensor.

Abstract: Methods, systems, and computer-readable media are disclosed herein combine randomization functionalities with the machine-learning prioritization of workflows for performance testing. In aspects, a primary workflow having a sequence of user interface steps is input. Testing workflows are generated that represent each variable position of unlocked steps in the sequence of the primary workflow while maintaining the sequential position of any locked steps. These testing workflows are then ingested to a machine learning model that identifies as subset of the testing workflows to prioritize over other. Specifically, testing workflows are prioritized that at least partially match sequence patterns in historical workflow data that is associated with vulnerable computer code. The subset is output and tested by testing engine to generate a report of any vulnerable computer code.

Abstract: A multi-lane transmitting apparatus includes lanes, and each lane includes a serializer circuit to convert parallel bits to serial bits. A clock signal generator generates a first clock signal having phases. A deserializer circuit converts serial bits to parallel bits. A Built-In Self-Test (BIST) circuit includes a signal generator circuit for generating a signal having bits in a defined pattern. A comparator circuit compares a pattern of bits of an output signal with the defined pattern. A BIST lane circuit monitors a status of the lanes. A BIST central circuit receives the status and determines if a number of lanes having an unmatched status is less than a threshold value. A phase extrapolator circuit adjusts a phase of the first clock signal when the number of the lanes is less than the threshold value.