Abstract: A power controller for a computer system capable of supporting multiple processor types. The power controller receives a voltage identification signal from the microprocessor and a microprocessor selection signal from a motherboard to provide a correct voltage specification signal and terminal voltage to the microprocessor. The invention also provides voltage specification signals and terminal voltages to the motherboard of a computer system that can support a multiple of processor types.

Abstract: A system and a method capable of automatically reading out the multiple value of clock frequency on system bus are provided. The system includes a central processing unit and a chipset. The central processing unit has a storage unit for holding a multiple value of clock frequency. The storage unit is capable of synchronizing with an external device through a serial initialization packet (SIP) protocol. The chipset attempts to synchronize with the central processing unit in a SIP protocol that uses a preset multiple value of clock frequency as a parameter. If synchronization between the central processing unit and the chipset cannot be established, the preset multiple value of clock frequency is changed and the SIP protocol is executed again. The multiple value of clock frequency is reset until synchronization is established. After synchronization, the multiple value of clock frequency in the central processing unit is retrieved and compared with the preset multiple value of clock frequency.

Abstract: A layout structure of a central processing unit (CPU) that supports two different package techniques, comprising a motherboard that comprises the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially places a top signal layer, a grounded layer, a power layer having a grounded potential, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer. Therefore, part of signals of the CPU that are coupled to the control chip can be placed on the bottom solder layer.

Abstract: A chipset to support multiple CPU's and a layout method thereof. Those independent signal lines for delivering high frequency clock signals of the chipset are isolated from using by other signals without being multiplexed. Trace length of the independent signal line is shorter than that of the others. The spaces between the independent signal line and others are also larger than that between other signal lines. Signal transmission quality is significantly upgraded because the high frequency clock signal is not multiplexed and isolated from others.

Abstract: A chip package structure having a substrate therein for accommodating a die. Power regions supplying power to various control units within the die are grouped together into at least two sections. At least one ? filter is used to isolate different power regions on the substrate so that cross interference of noise signals are reduced and stability of the chip is improved. The ? filter is positioned close to one of the corners of the substrate so that the layout of wiring on the substrate is facilitated.

Abstract: An integrated testing method is proposed to perform a test procedure on a number of computer components, concurrently, in a multitasking manner through software simulation. In this method, an initialization procedure is first performed to specify the total number of simulated operations, the FIFO buffer size, the command sequence, and the start time of operation. It is a characteristic feature of this integrated testing method that the test procedure is performed concurrently in a multitasking manner on all the components under test to operate in response to each command from the command sequence. In the event that two or more of the components under test are competing for the same resource, an arbiter is activated to perform arbitration for these competing components.

Abstract: A motherboard utilizing a single-channel memory controller to control multiple DRAMs. The motherboard includes a first memory slot, a second memory slot, and a single-channel memory controller. The memory controller is connected to the first memory slot and the second memory slot respectively through a first bus and a second bus.

Abstract: An I/O pad has a data transmitting circuit, a data monitoring control circuit, and a control selection circuit. The control selection circuit controls the data transmitting circuit at the control end, so as to enable or disable the transmission. When it is enabled, data in the data transmitting circuit are exported to a receiving circuit. When it is disabled, data exportation stops. The data monitoring circuit receives signals of the data transmission circuit and export signals to the control selection circuit. The data monitoring circuit judges whether the data transmission is under a stable condition. If it is not yet, an unstable signal is exported to a first input end of the control selection circuit. A second input end of the control selection circuit receives an output enabling signal. The output end of the control selection circuit is connected to the control end of the data transmitting circuit.

Abstract: The graphics display architecture provided by the present invention comprises an AGP slot, a PCIE slot, and a control chip set. The control chip set comprises a plurality of multi-defined pins, which are electrically coupled to the first pins of the AGP slot and the second pins of the PCIE slot simultaneously. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with AGP interface specification, the multi-defined pins serve to send/receive the signal complied with AGP interface specification. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with the Gfx interface, the multi-defined pins serve to send/receive the signal complied with the Gfx interface. When the second graphics adapter is plugged in the PCIE slot, the multi-defined pins serve to send/receive the signal complied wit the PCIE interface specification.

Abstract: The present invention is a placement that is utilized in a 4 layers motherboard and a main bridge chip substrate. The layout adds a placement of the power rings and the power paths on the top signal layer and the bottom solder layer of the main bridge chip on the motherboard, the second layer and the third layer are planned as grounded layers, so that all signals on the top signal layer and the bottom solder layer on the motherboard can easily refer to the grounded layer. The layout of the power ring and the power path on the top signal layer on the motherboard is symmetrical to the layout of the power ring and the power path on the bottom solder layer on the motherboard, and all power paths couple to the corresponding power rings. The power bonding pads/solder balls are arranged on the area where the power rings and the power paths pass through, and the moderate quantity of the grounded bonding pads are arranged on the both sides of the power paths.

Abstract: A data processing system including a control chip, a central processing unit and a printed circuit board is provided. In the data processing system, the printed circuit board not only supports the control chip and the central processing unit, but also serves as an interface for transferring signals between the control chip and the central processing unit. Critical signals can be transmitted from the central processing unit to the control chip via the printed circuit with a better return path.

Abstract: An integrated circuit includes voltage identification (VID) logic and frequency identification logic (FID) for a CPU, as well as power good circuitry for indicating the suitability of electrical power supplies. A VID output signal to control a core voltage provided to the CPU is generated according to an input VID signal provided by the CPU, a sleep state signal, and a CPU mobility-type signal. FID, VID and power detection logic all level shift signals as required for external devices. A programmable table enables overriding of output FID and VID values.

Abstract: A layout structure of a central processing unit (CPU) that supports two different package techniques, comprising a motherboard that comprises the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially places a top signal layer, a grounded layer, a power layer having a grounded potential, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer. Therefore, part of signals of the CPU that are coupled to the control chip can be placed on the bottom solder layer.

Abstract: An I/O pad has a data transmitting circuit, a data monitoring control circuit, and a control selection circuit. The control selection circuit controls the data transmitting circuit at the control end, so as to enable or disable the transmission. When it is enabled, data in the data transmitting circuit are exported to a receiving circuit. When it is disabled, data exportation stops. The data monitoring circuit receives signals of the data transmission circuit and export signals to the control selection circuit. The data monitoring circuit judges whether the data transmission is under a stable condition. If it is not yet, an unstable signal is exported to a first input end of the control selection circuit. A second input end of the control selection circuit receives an output enabling signal. The output end of the control selection circuit is connected to the control end of the data transmitting circuit.

Abstract: An integrated testing method is proposed to perform a test procedure on a number of computer components, concurrently, in a multitasking manner through software simulation. In this method, an initialization procedure is first performed to specify the total number of simulated operations, the FIFO buffer size, the command sequence, and the start time of operation. It is a characteristic feature of this integrated testing method that the test procedure is performed concurrently in a multitasking manner on all the components under test to operate in response to each command from the command sequence. In the event that two or more of the components under test are competing for the same resource, an arbiter is activated to perform arbitration for these competing components.

Abstract: A structure and a method for an extended bus and a bridge in the extended bus are disclosed. The structure of the extended bus has a first accelerated graphics port bus, a first bridge, a second accelerated graphics port bus and a first extended bus. The first bridge performs a compatible mutual conversion of the signal and data between the first accelerated graphics port bus and the first extended bus or the second accelerated graphics port bus, so that the first accelerated graphics port bus is extended for use. The invention extends and expands the current available high-speed and wide-bandwidth accelerated graphics port bus to obtain one or more extended buses. The data path through the south bridge chip is thus avoided. Furthermore, more expansion slots are provided to the system, and the flexibility of expanding the computer system is increased.

Abstract: A mother board and a computer system capable of flexibly using the SDRAM and the DDRAM. The mother board has several memory module slots, a voltage comparator, a clock generator and a chip set. Each of the memory module slots comprises a reference voltage pin, and the reference voltage pins of the memory module slots are connected to each other in parallel. The voltage comparator is coupled to the reference voltage pins of the memory module slots to detect whether the voltage at the reference voltage pin is equivalent to a reference voltage. The clock generator is coupled to an output of the voltage comparator. When the voltage at the reference voltage pin is equal to the reference voltage, a differential clock signal is generated, and when the votlage is different from the reference voltage, a normal clock signal is generated. The chip set is coupled to the output of the voltage comparator. When the voltage is equal to the reference voltage, the chip set is operated under a double data rate mode.

Abstract: A layout structure of a central processing unit (CPU) that supports two different package techniques, having a motherboard that comprising the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially placed a top signal layer, a grounded layer, a power layer having an operating potential area and a grounded potential area, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer.

Abstract: An integrated circuit (IC) package structure with heat dissipation design. The IC chip is disposed on a package substrate and a power ring structure surrounds the chip. Due to the relatively large surface area of the power ring structure near the high heat zone of the IC chip, the contact area between the power ring structure and package substrate is enlarged. The power ring structure is connected to the isoelectric conductive layer of a multi-layer circuit board via an electric connection path, thereby enhancing heat dissipation.

Abstract: A wire bonding BGA package. On a conductive metal layer of a substrate used for carrying a die, a power ring for providing an operating voltage to a core circuit of the die is disposed in the inner side of a power ring for providing an operating voltage to an input/output circuit of the die. When the die is packaged by flip chip packaging instead of wire bonding packaging, the power bailout assignment of the BGA package is unchanged and is suitable for matching with an original circuit board used for the wire bonding BGA package. In addition, the present invention provides a flip chip BGA package. When the die is packaged by wire bonding packaging instead of flip chip packaging, the power bailout assignment of the BGA package is unchanged and is suitable for matching with an original circuit board used for the flip chip BGA package.

Abstract: A processing apparatus includes a processing chamber and an insertion jig for inserting an object to be processed into the processing chamber. The processing chamber and the insertion jig are adapted to be individually movable relative to a heating section, so that the operation of loading and unloading the object into and from the processing chamber effected by the insertion jig is conducted outside the heating section, thereby preventing the outside air from being induced to enter the heated processing chamber, together with the object of the processing, and thus avoiding the occurrence of various problems, for example, the object of processing being disorderly oxidized by the oxygen contained in the outside air, and the foreign matter contained in the outside air being undesirably attached to the surface of the object, so as to obtain excellent processing results.