Abstract: An apparatus for providing both supports including synchronous dynamic random access memory module and the double data rate dynamic random access memory module is provided. A motherboard can support standard synchronous dynamic random access memory and dual data rate dynamic random access memory by using the disable and enable functions of the terminator. The invention reduces manufacturing production waste due to complex fabrication process of memory module. In addition, the trouble of upgrading the computer by consumer can be eliminated.

Abstract: A terminating circuit module and a computer system using the same, in which a voltage regulator and a plurality of pull-up resistors can be provided on the terminating circuit module by the mainboard producer to reduce the area of the printed circuit board of the mainboard. Also, a nonvolatile memory can be provided on the terminating circuit module to store the information representing such terminating circuit module. The computer can automatically read the configuration of the memory and the terminating circuit module such as the slotted positions for the terminating circuit module and the memory module to prevent users from using the terminating circuit module in an incorrect way.

Abstract: An integrated circuit pin layout for packaging a chip is provided. A layout for the pins in an integrated circuit package is provided to optimize most of the relative reference voltages or relative reference grounds. The power pins are put together after a definite number is exceeded and neighboring power pins are positioned perpendicular to the edge of the substrate board inside the integrated circuit package. Ultimately, the connection channels of the relative reference voltage layer or the relative power circuit layer (also called the relative reference ground layer) are widened. Consequently, high-frequency impedance of the substrate board is lowered, number of through holes is reduced, number of voltage-stabilizing capacitors is increased and power source is stabilized.

Abstract: A control circuit, a chipset and a method capable of saving the terminal resistors on a motherboard. Through the determination of connection of a pull-up enable line to a first voltage source Vdd via a resistor, an equivalent resistance is set between the source terminal and the drain terminal of a field effect transistor. The equivalent resistance is almost identical to the terminal resistor and hence can replace the resistor on the motherboard. When the pull-up enable line is connected to the first voltage source Vdd via a resistor, an equivalent resistance of about 45-60 &OHgr; is established between the source and drain terminal of the field effect transistor. The equivalent resistance is connected in parallel with an input/output pad and a second voltage source Vtt to replace the original externally connected terminal resistor rt2 at the other end of the bus.

Abstract: A computer main board having a plurality of 184-lead memory module slots and a plurality of 168-lead memory module slots, a computer system, a terminal circuit module and memory modules that can be used in the main board and computer system. A control chipset on the main board can be preset so that any particular memory module on a memory module slot can be selected to operate in a special write mode. In other words, whether the write data has 64-bit length or not, a complete 64-bit data according to 64-bit (QW) block division is first read out and modified before writing the complete 64-bit data, In this invention, the wiring layout of the main board does not have to follow the signal line bit sequence. Al that is required is to connect each independent data line of the 168-pin slot with each independent data line of the 184-pin memory module slot.

Abstract: A control chipset having dual-definition data pins capable of reducing circuit layout to memory module slots. Using dual-definition data pins of the control chipset and multiplexing/de-multiplexing devices, the control chipset is able to sense the particular type of memory modules plugged into memory slots automatically and hence assigning the function to each data pin accordingly. Consequently, circuit layout from the control chipset to the data pins of far off memory slots is simplified and overall circuit length is greatly reduced.

Abstract: A memory control system for controlling write-enable signals. The memory control system has a first memory slot having a write-enable pin thereon, a second memory slot having a first write-enable pin and a second write-enable pin thereon and a control chipset having a write-enable pin and a dual-purpose write-enable/memory-parity-data pin thereon. The write-enable pin of the control chipset is connected to the write-enable pin of the first memory slot and the first write-enable pin of the second memory slot. The write-enable/memory-parity-data pin of the control chipset is connected to the second write-enable pin of the second memory slot. In this invention, since the design of the write-enable system is more flexible, length of trace line on a computer board can be greatly reduced. In addition, the system permits the incorporation of one cycle (1T) timing into design of memory access commands.

Abstract: A terminating circuit module and a computer system using the same, in which a voltage regulator and a plurality of pull-up resistors can be provided on the terminating circuit module by the mainboard producer to reduce the area of the printed circuit board of the mainboard. Also, a nonvolatile memory can be provided on the terminating circuit module to store the information representing such terminating circuit module.

Abstract: A feedback system capable of accommodating different memory module loading. The feedback system utilizes the signal received by the data strobe feedback pin of a control chipset to simulate or to obtain memory module loading information so that timing of the data signal and data strobe signal can be adjusted accordingly. Therefore, data can be accurately written to or read from the memory module. The embodiment of this invention includes using a variable reference voltage source and a comparator to adjust the timing of the signal to the data strobe feedback pin, using independent simulating loads circuit and specially designed memory module with simulating load, and using a data strobe signal circuit that includes complete memory module loading.

Abstract: A system can produce a suitable voltage for powering the memory modules plugged into the memory module slots of a motherboard. A power-good signal is issued when the motherboard is powered up. A power safety device on the motherboard then issues a 2.5V to the memory module slot. If DDR DRAM type of memory modules are not detected after a while, the power safety device will turn off the 2.5V supply and provide a 3.3V, which is suitable for SDRAM type memory modules. This invention avoids sending a 3.3V to DDR DRAM modules, thereby burning the memory chip. The presence of DDR DRAM modules can be detected by a general-purpose input/output port through accessing the recorded data in the EEPROM of the memory module. Alternatively, memory module type can be determined by sending out a low-current pulse signal to the memory module slot. Hence, a suitable voltage source is automatically provided to power the memory modules in the slots.

Abstract: A buffer for varying data access speed. Combining the buffer with a memory such as a double data rate synchronous dynamic random access memory, the data transmission rate of a memory system can be enhanced. The buffer is coupled with a control chip set and several memory modules to provide functions of data analysis and assembly to satisfy a two-way data transmission interface and to obtain a higher data transmission rate. The buffer also has the function of isolating the electric connection between two sides. A single signal interface from a memory module can be converted to a complementary source synchronous signal by the buffer, so that a high-speed data transmission can be achieved. A memory system can apply several of such buffers to achieve an even higher data transmission speed.

Abstract: An integrated circuit (IC) mounting board is provided for use to mount an IC module and as least one bypass capacitor thereon. The IC mounting board allows the layout of the wiring between the IC module and the circuit lines on the IC mounting board to be more convenient to carry out. Moreover, the IC mounting board allows the bypass capacitor to provide the bypass effect more effectively.

Abstract: A temperature sensing system for monitoring and controlling temperatures of various peripheral devices inside a notebook type of computer. The temperature sensing system uses a thermistor as a temperature sensor. The thermistor is positioned around a peripheral device and forms a potential divider circuit with another resistor. Next, the voltage produced by the divider circuit is fed to a voltage detection pin of a chipset. Inside the chipset, the divider voltage can be compared with a reference so that appropriate action can be taken to cool down a particular peripheral device. In addition, the temperature sensor of this invention can be placed anywhere inside a notebook computer including the area surrounding the peripheral device or even inside the peripheral device. Moreover, no additional control chips for operating those temperature sensors arc needed, and hence production cost can be lowered.

Abstract: A device which uses an NOP command to share a memory bus. The device includes a chipset, wherein a peripheral control circuit and a memory control circuit are integrated into the chipset. The peripheral control circuit and the memory control circuit share a plurality of pins in the chipset. A memory bus is connected to the chipset by the pins in the chipset. A peripheral device receives data sent from the peripheral control circuit through the memory bus. A drive circuit is connected to the memory bus. A main memory is connected to the memory bus.

Abstract: A computer chipset having reduced peripheral pins for accessing a conventional ROM in a computer system is disclosed. There is a switching circuit within the chipset. When the computer is turned on, a booting control circuit activates a booting enabling signal, so that booting programs can be accessed from the ROM through the switching circuit and are executed in a main processor. Subsequently, contents stored in the ROM are moved to a main memory and the booting enabling signal is inactivated by the booting control circuit to allow a peripheral control circuit to communicate with peripheral devices. In this way, chipset having a low pin count (LPC) interface circuit can share the peripheral pins of the chipset to access the conventional ROMs, so that the production costs can be reduced.

Abstract: A method and circuit is provided for safeguarding the data stored in a CMOS RAM (Complementary Metal-Oxide Semiconductor Random Access Memory) unit in a computer system, such as an IBM-compatible personal computer (PC), when the battery unit used to power the CMOS RAM unit is below working level. By this method and circuit, when the PC is powered off, the current power level of the battery unit is detected to see whether it is below working level; if yes, the main power of the PC is turned on; then the data currently stored in the CMOS RAM unit are moved to a backup-data storage unit such as the hard disk; and after this, the main power is turned off again. At the next time the PC is powered on, the data currently stored in the backup-data storage unit are moved back to the CMOS RAM unit; and after this, a message is displaying on the monitor screen requesting the user to replace the CMOS RAM battery with a new one.

Abstract: A power surge detection device is disclosed to investigate if there is any power surge occurring to a main processor in a computer system. When the width or frequency of power surges detected jeopardize the normal operation of the computer system, an alerting signal, for example, an interrupt signal or a power management signal, is sent to the main processor to intervene in the normal operation of the computer system so as to avoid the power instability period.

Abstract: An input/output buffer capable of supporting multiple transmission logic bus specifications. The input/output buffer has a coordinating controller, a logic control circuit, a first transistor, a second transistor, a first resistor element, and a second resistor element. The logic control circuit picks up a microprocessor-type signal to determine the type of microprocessors used. According to the microprocessor type, conductivity of the first transistor, the second transistor, the first resistor element and the second resistor element are reassigned to fit the particular logic bus specification of the microprocessor. Hence, a single chipset on a main circuit board is able to accommodate various types of microprocessors.

Abstract: An input/output buffer capable of supporting multiple transmission logic bus specifications. The input/output buffer has a coordinating controller, a logic control circuit, a first transistor, a second transistor, a first resistor element, and a second resistor element. The logic control circuit picks up a microprocessor-type signal to determine the type of microprocessors used. According to the microprocessor type, conductivity of the first transistor, the second transistor, the first resistor element and the second resistor element are reassigned to fit the particular logic bus specification of the microprocessor. Hence, a single chipset on a main circuit board is able to accommodate various types of microprocessors.

Abstract: A voltage-switching regulator with built-in voltage-switching module is provided, which is capable of supplying a terminal voltage to a memory unit operating under DDR (DRAM of Double Rate) mode. The voltage-switching regulator is implemented as a single IC chip with a built-in voltage-switching module, and is capable of generating a terminal voltage in response to an input reference voltage and transferring the terminal voltage via a transmission logic line to the memory unit operating under DDR mode. The terminal voltage is pulled up when the voltage-switching module supplies a drive current and is pulled down when the voltage-switching module supplies a sink current. This allows the memory unit to be operated under DDR mode.