Abstract: A method of refreshing DRAM. The method of the invention utilizes the time, in which CPU is executing a cache hit cycle, an input/output cycle, an interrupt acknowledge cycle or an idle cycle, to perform a least one refresh cycle for refreshing DRAM. It uses the time, in which CPU does not access DRAM, to perform the refresh cycle. Besides, it needs to insert the rest of the refresh cycles, which are required to be accomplished during a fixed time period, to replace any operational cycle of DRAM before the end of the fixed time period comes.

Abstract: A high-performance and cost-effective cache memory system is provided for use in conjunction with a high-speed computer system. The cache memory system is used on a computer system having a central processing unit (CPU) of the type having a back-off function that can be activated to temporarily halt the CPU when receiving a back-off signal. The cache memory system is capable of enabling the back-off signal in the event that the data read request signal from the CPU is determined to be a miss. During the back-off duration of the CPU, the requested data are moved from the primary memory unit to the cache memory module. This feature allows the overall performance of the computer system to be high even though a low-speed tag random-access memory (RAM) is used in the cache memory system, allowing the computer system to be highly cost-effective to use with high performance.

Abstract: A setting/driving circuit is provided for use in conjunction with an IC logic unit, such as a CPU having one or more multi-function pins, to provide two or more sets of data, such as a set of parameter data and a set of control data, via the same multi-function pins to the CPU. The setting/driving circuit includes a tri-state buffer and a parameter setting unit composed of two resistors and a switch, such as a jumper. When the tri-state buffer is disabled, the parameter data set by the switch is transferred to the multi-function pin of the CPU. On the other hand, when the tri-state buffer is enabled, the input data to the input port of the tri-state buffer is transferred to the multi-function pin of the CPU. The tri-state buffer can be integrated within the chip set without having to increase the total number of pins on the chip set so that the layout complexity on the motherboard can be simpler and thus easier to assemble compared to the prior art.

Abstract: The present invention provides a computer motherboard having an Intel P54C compatible processor socket and a control chip having specifically arranged data pins and address pins which allows a short signal path arrangement from the processor socket to a cache tap RAM and a cache data RAM. The computer motherboard comprises a four-layer printed circuit board, a processor socket, a cache data RAM, a cache tag RAM, and a control chip. All these components are connected by using a high-order-bit data bus, a low-order-bit data bus, and an address bus through the top and bottom layers of the circuit board. The cache data RAM is positioned on the right side of the processor socket. The control chip is positioned on the top side of the cache data RAM and on the top-right side of the processor socket.

Abstract: An impedance adjusting apparatus of a controlling chip on a computer mainboard. When a computer is turned on, BIOS automatically detects the actual usage of the memory sockets, and then sends corresponding control signals to adjust the impedance of the impedance adjusting apparatus for a better impedance matching between the controlling chip and the memory sockets. The signal reflection is dramatically reduced and the operation bandwidth is widened.

Abstract: A signal converter with a dynamically adjustable reference voltage according to the invention, which can receive different qualities of signals. The signal converter includes an input circuit and a reference voltage generator. The input circuit converts a first digital signal, such as a GTL+ signal, into a second digital signal, such as a TTL or CMOS signal, based on an adjustable reference voltage generated by the reference voltage generator. When a control circuit needs to receive the first digital signal from outside via the input circuit, the control circuit can adjust the reference voltage by controlling the reference voltage generator so as to receive the first digital signal with a different quality.

Abstract: A power-source-switching device automatically capable of directing power from a battery or an external power source to an all-time circuit. When the external power source is connected, a switching circuit directs the external power source to the all-time circuit. On the other hand, when the external power source is disconnected, the switching circuit is able to direct power from the battery to the all-time circuit. Since the conventional diode connection is replaced by a switching circuit, a voltage drop across the diode due to forward bias is avoided. Consequently, the battery can work at a lower voltage level, thereby extending the working life of a battery.