Patents by Inventor Nam-Kyeong Kim
Nam-Kyeong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8163614Abstract: A method for fabricating a NAND type flash memory device includes defining a select transistor region and a memory cell region in a semiconductor substrate, forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over a semiconductor substrate, etching the dielectric layer, thereby forming an opening exposing the floating gate conductive layer, forming a low resistance layer in the opening, forming a control gate conductive layer over the semiconductor substrate, and etching the control gate conductive layer, the dielectric layer, the floating gate conductive layer, and the tunnel insulating layer to form gate stacks of memory cells and source/drain select transistors.Type: GrantFiled: November 30, 2010Date of Patent: April 24, 2012Assignee: Hynix Semiconductor Inc.Inventors: Nam-Kyeong Kim, Won Sic Woo
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Publication number: 20120051129Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a nonvolatile memory device having a recess structure and methods of fabricating same.Type: ApplicationFiled: August 26, 2010Publication date: March 1, 2012Applicant: Numonyx B.V.Inventors: Nam-Kyeong Kim, Jeong-Min Choi
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Patent number: 8106448Abstract: A method of manufacturing a NAND flash memory device. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can be increased and disturbance can be reduced. It is therefore possible to improve the reliability and yield of devices.Type: GrantFiled: April 19, 2010Date of Patent: January 31, 2012Assignee: Hynix Semiconductor Inc.Inventors: Jae Chul Om, Nam Kyeong Kim
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Publication number: 20120008395Abstract: A nonvolatile memory device includes memory cell blocks each configured to comprise memory cells erased by an erase voltage, supplied to a word line, and a bulk voltage supplied to a bulk, a bias voltage generator configured to generate a first erase voltage, having a first pulse width and a first amplitude, in order to perform the erase operation of the memory cells and a second erase voltage, having a second pulse width narrower than the first pulse width and a second amplitude lower than the first amplitude, in order to perform an additional erase operation if an unerased memory cell is detected after the erase operation is performed, and a bulk voltage generator configured to generate the bulk voltage.Type: ApplicationFiled: July 5, 2011Publication date: January 12, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Nam Kyeong Kim, Kyoung Chul Yang, Young Jin Woo, Tae Hyun Kim
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Publication number: 20120008392Abstract: A nonvolatile memory device includes a plurality of memory blocks, a plurality of erasure detection units provided at the plurality of memory blocks, respectively, and configured to each detect erasure of the respective memory blocks, and a control unit configured to determine that a memory block is a bad memory block when a number of erasure operations performed on the memory block as detected by the respective erasure detection unit is greater than a reference value.Type: ApplicationFiled: September 9, 2010Publication date: January 12, 2012Inventors: Nam-Kyeong KIM, Jung-Min Choi
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Publication number: 20110171797Abstract: A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.Type: ApplicationFiled: March 22, 2011Publication date: July 14, 2011Applicant: Hynix Semiconductor Inc.Inventors: Jae Chul OM, Nam Kyeong Kim, Se Jun Kim
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Patent number: 7944758Abstract: A method for performing a copy-back operation in a non-volatile memory device includes: measuring and recording a maximum program voltage used to program a part of target data to copy-back when a copy-back command is inputted; and performing a copy-back operation using the recorded maximum program voltage.Type: GrantFiled: June 26, 2009Date of Patent: May 17, 2011Assignee: Hynix Semiconductor Inc.Inventors: Nam-Kyeong Kim, Jung-Min Choi
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Publication number: 20110070706Abstract: A method for fabricating a NAND type flash memory device includes defining a select transistor region and a memory cell region in a semiconductor substrate, forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over a semiconductor substrate, etching the dielectric layer, thereby forming an opening exposing the floating gate conductive layer, forming a low resistance layer in the opening, forming a control gate conductive layer over the semiconductor substrate, and etching the control gate conductive layer, the dielectric layer, the floating gate conductive layer, and the tunnel insulating layer to form gate stacks of memory cells and source/drain select transistors.Type: ApplicationFiled: November 30, 2010Publication date: March 24, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Nam-Kyeong Kim, Won Sic Woo
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Patent number: 7910430Abstract: A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.Type: GrantFiled: March 4, 2008Date of Patent: March 22, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae Chul Om, Nam Kyeong Kim, Se Jun Kim
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Patent number: 7863671Abstract: A method for fabricating a NAND type flash memory device includes defining a select transistor region and a memory cell region in a semiconductor substrate, forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over a semiconductor substrate, etching the dielectric layer, thereby forming an opening exposing the floating gate conductive layer, forming a low resistance layer in the opening, forming a control gate conductive layer over the semiconductor substrate, and etching the control gate conductive layer, the dielectric layer, the floating gate conductive layer, and the tunnel insulating layer to form gate stacks of memory cells and source/drain select transistors.Type: GrantFiled: June 28, 2007Date of Patent: January 4, 2011Assignee: Hynix Semiconductor Inc.Inventors: Nam-Kyeong Kim, Won Sic Woo
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Patent number: 7851311Abstract: Non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and the devices can pass the limit in terms of layout, whereby channel length can be controlled. The non-volatile memory device includes gate lines formed in one direction on a semiconductor substrate in which trenches are formed, wherein the gate lines gap-fill the trenches, a dielectric layer formed between the semiconductor substrate and the gate lines, bit separation insulating layers formed between the semiconductor substrate and the dielectric layer under the trenches, and isolation structures formed by etching the trenches, and the dielectric layer and the semiconductor substrate between the trenches in a line form vertical to the gate lines and gap-filling an insulating layer.Type: GrantFiled: July 2, 2009Date of Patent: December 14, 2010Assignee: Hynix Semiconductor Inc.Inventors: Nam-Kyeong Kim, Jae Chul Om
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Patent number: 7800946Abstract: A flash memory device includes a plurality of memory cell blocks, a control unit, a program speed calculation unit, a voltage generator and a block select unit. Each memory cell block includes a string having a drain select transistor, a plurality of memory cells, a novel cell and a source select transistor. The control unit generates a block select signal in response to an address signal and generates an operation control signal in response to a command signal. The program speed calculation unit decides a level of an initial program voltage based on threshold voltages detected after a program operation of the novel cells. The voltage generator generates operating voltages including the initial program voltage of the level according to the operation control signal. The block select unit transfers the operating voltages to a memory cell block corresponding to the block select signal.Type: GrantFiled: May 30, 2008Date of Patent: September 21, 2010Assignee: Hynix Semiconductor Inc.Inventors: Nam Kyeong Kim, Ju Yeab Lee
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Publication number: 20100200902Abstract: A method of manufacturing a NAND flash memory device. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can be increased and disturbance can be reduced. It is therefore possible to improve the reliability and yield of devices.Type: ApplicationFiled: April 19, 2010Publication date: August 12, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Jae Chul Om, Nam Kyeong Kim
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Publication number: 20100182845Abstract: A method for performing a copy-back operation in a non-volatile memory device includes: measuring and recording a maximum program voltage used to program a part of target data to copy-back when a copy-back command is inputted; and performing a copy-back operation using the recorded maximum program voltage.Type: ApplicationFiled: June 26, 2009Publication date: July 22, 2010Inventors: Nam-Kyeong Kim, Jung-Min Choi
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Patent number: 7727839Abstract: A method of manufacturing a NAND flash memory device is disclosed. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can be increased and disturbance can be reduced. It is therefore possible to improve the reliability and yield of devices.Type: GrantFiled: December 28, 2006Date of Patent: June 1, 2010Assignee: Hynix Semiconductor Inc.Inventors: Jae Chul Om, Nam Kyeong Kim
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Patent number: 7623385Abstract: Provided is a method of reading a flash memory device for depressing read disturb. According to the method, a first voltage is applied to a gate of the drain select transistor to turn on the drain select transistor, and a read voltage is applied to a gate of a selected transistor among the plurality of memory cells. Then, a pass voltage is applied to gates of unselected transistors among the plurality of memory cells. Furthermore, when the pass voltage is applied, a first pass voltage is applied and then a second pass voltage is applied after an elapse of a predetermined time following the applying of the first pass voltage. The second pass voltage has a level different from that of the first pass voltage.Type: GrantFiled: December 27, 2007Date of Patent: November 24, 2009Assignee: Hynix Semiconductor Inc.Inventors: Nam Kyeong Kim, Ju Yeab Lee, Keum Hwan Noh
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Publication number: 20090269895Abstract: Non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and the devices can pass the limit in terms of layout, whereby channel length can be controlled. The non-volatile memory device includes gate lines formed in one direction on a semiconductor substrate in which trenches are formed, wherein the gate lines gap-fill the trenches, a dielectric layer formed between the semiconductor substrate and the gate lines, bit separation insulating layers formed between the semiconductor substrate and the dielectric layer under the trenches, and isolation structures formed by etching the trenches, and the dielectric layer and the semiconductor substrate between the trenches in a line form vertical to the gate lines and gap-filling an insulating layer.Type: ApplicationFiled: July 2, 2009Publication date: October 29, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Nam Kyeong Kim, Jae Chul Om
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Patent number: 7573089Abstract: Non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and the devices can pass the limit in terms of layout, whereby channel length can be controlled. The non-volatile memory device includes gate lines formed in one direction on a semiconductor substrate in which trenches are formed, wherein the gate lines gap-fill the trenches, a dielectric layer formed between the semiconductor substrate and the gate lines, bit separation insulating layers formed between the semiconductor substrate and the dielectric layer under the trenches, and isolation structures formed by etching the trenches, and the dielectric layer and the semiconductor substrate between the trenches in a line form vertical to the gate lines and gap-filling an insulating layer.Type: GrantFiled: December 6, 2006Date of Patent: August 11, 2009Assignee: Hynix Semiconductor Inc.Inventors: Nam Kyeong Kim, Jae Chul Om
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Publication number: 20090161432Abstract: A flash memory device includes a plurality of memory cell blocks, a control unit, a program speed calculation unit, a voltage generator and a block select unit. Each memory cell block includes a string having a drain select transistor, a plurality of memory cells, a novel cell and a source select transistor. The control unit generates a block select signal in response to an address signal and generates an operation control signal in response to a command signal. The program speed calculation unit decides a level of an initial program voltage based on threshold voltages detected after a program operation of the novel cells. The voltage generator generates operating voltages including the initial program voltage of the level according to the operation control signal. The block select unit transfers the operating voltages to a memory cell block corresponding to the block select signal.Type: ApplicationFiled: May 30, 2008Publication date: June 25, 2009Applicant: Hynix Semiconductor Inc.Inventors: Nam Kyeong Kim, Ju Yeab Lee
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Publication number: 20080298127Abstract: Provided is a method of reading a flash memory device for depressing read disturb. According to the method, a first voltage is applied to a gate of the drain select transistor to turn on the drain select transistor, and a read voltage is applied to a gate of a selected transistor among the plurality of memory cells. Then, a pass voltage is applied to gates of unselected transistors among the plurality of memory cells. Furthermore, when the pass voltage is applied, a first pass voltage is applied and then a second pass voltage is applied after an elapse of a predetermined time following the applying of the first pass voltage. The second pass voltage has a level different from that of the first pass voltage.Type: ApplicationFiled: December 27, 2007Publication date: December 4, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Nam Kyeong Kim, Ju Yeab Lee, Keum Hwan Noh