Patents by Inventor Nam-Kyeong Kim
Nam-Kyeong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7456466Abstract: A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.Type: GrantFiled: June 2, 2006Date of Patent: November 25, 2008Assignee: Hynix Semiconductor Inc.Inventors: Jae Chul Om, Nam Kyeong Kim, Se Jun Kim
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Patent number: 7410881Abstract: A method of manufacturing a flash memory device includes etching an insulating layer provided over a substrate to form a contact hole to define a contact hole exposing a junction region formed on the substrate. The contact hole is filled with a first conductive material, the first conductive material contacting the junction region and extending above an upper surface of the contact hole. The first conductive material is etched to partly fill the contact hole, so that the first conductive material fills a lower portion of the contact hole, wherein an upper portion of the contact hole remains not filled due to the etching of the first conductive material, wherein the etched first conductive material defines a contact plug. A first dielectric layer and a second dielectric layer are formed over the contact plug, thereby filling the upper portion of the contact hole. Part of the first and second dielectric layers is etched to expose the contact plug and the upper portion of the contact hole.Type: GrantFiled: December 29, 2006Date of Patent: August 12, 2008Assignee: Hynix Semiconductor Inc.Inventors: Sun Mi Park, Yoo Nam Jeon, Nam Kyeong Kim, Se Jun Kim
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Publication number: 20080153227Abstract: A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.Type: ApplicationFiled: March 4, 2008Publication date: June 26, 2008Applicant: Hynix Semiconductor Inc.Inventors: Jae Chul Om, Nam Kyeong Kim, Se Jun Kim
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Publication number: 20080106942Abstract: A method for fabricating a NAND type flash memory device includes defining a select transistor region and a memory cell region in a semiconductor substrate, forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over a semiconductor substrate, etching the dielectric layer, thereby forming an opening exposing the floating gate conductive layer, forming a low resistance layer in the opening, forming a control gate conductive layer over the semiconductor substrate, and etching the control gate conductive layer, the dielectric layer, the floating gate conductive layer, and the tunnel insulating layer to form gate stacks of memory cells and source/drain select transistors.Type: ApplicationFiled: June 28, 2007Publication date: May 8, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Nam-Kyeong Kim, Won Sic Woo
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Publication number: 20070264775Abstract: Non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and the devices can pass the limit in terms of layout, whereby channel length can be controlled. The non-volatile memory device includes gate lines formed in one direction on a semiconductor substrate in which trenches are formed, wherein the gate lines gap-fill the trenches, a dielectric layer formed between the semiconductor substrate and the gate lines, bit separation insulating layers formed between the semiconductor substrate and the dielectric layer under the trenches, and isolation structures formed by etching the trenches, and the dielectric layer and the semiconductor substrate between the trenches in a line form vertical to the gate lines and gap-filling an insulating layer.Type: ApplicationFiled: December 6, 2006Publication date: November 15, 2007Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Nam Kyeong Kim, Jae Chul Om
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Publication number: 20070207580Abstract: A method of manufacturing a flash memory device includes etching an insulating layer provided over a substrate to form a contact hole to define a contact hole exposing a junction region formed on the substrate. The contact hole is filled with a first conductive material, the first conductive material contacting the junction region and extending above an upper surface of the contact hole. The first conductive material is etched to partly fill the contact hole, so that the first conductive material fills a lower portion of the contact hole, wherein an upper portion of the contact hole remains not filled due to the etching of the first conductive material, wherein the etched first conductive material defines a contact plug. A first dielectric layer and a second dielectric layer are formed over the contact plug, thereby filling the upper portion of the contact hole. Part of the first and second dielectric layers is etched to expose the contact plug and the upper portion of the contact hole.Type: ApplicationFiled: December 29, 2006Publication date: September 6, 2007Applicant: Hynix Semiconductor Inc.Inventors: Sun Mi Park, Yoo Nam Jeon, Nam Kyeong Kim, Se Jun Kim
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Publication number: 20070155098Abstract: A method of manufacturing a NAND flash memory device is disclosed. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can be increased and disturbance can be reduced. It is therefore possible to improve the reliability and yield of devices.Type: ApplicationFiled: December 28, 2006Publication date: July 5, 2007Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Jae Chul Om, Nam Kyeong Kim
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Publication number: 20050006683Abstract: The present invention provides a ferroelectric memory device capable of suppressing a defect generation due to a charge impact and a method for fabricating the same. The ferroelectric memory device includes: a semiconductor substrate on which a transistor is formed; a semiconductor substrate structure having a transistor; a lower electrode formed on an interfacial insulation layer and connected to a source/drain region of the transistor; an isolating insulation layer on the interfacial insulation layer; a ferroelectric layer covering the isolating insulation layer and lower electrode; an oxygen vacancy compensation layer being formed on the ferroelectric layer and compensating an oxygen vacancy caused by deoxidization of a composition of the ferroelectric layer; and an upper electrode formed on the oxygen vacancy compensation layer.Type: ApplicationFiled: July 27, 2004Publication date: January 13, 2005Inventors: Nam-Kyeong Kim, Soon-Yong Kweon, Seung-Jin Yeom
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Patent number: 6815225Abstract: In the method for forming a capacitor of a nonvolatile semiconductor memory device, a TaON glue layer is formed over a semiconductor substrate, and a lower electrode is formed on the TaON glue layer. A ferroelectric film is then formed on the lower electrode, and an upper electrode is formed on the ferroelectric film.Type: GrantFiled: June 3, 2003Date of Patent: November 9, 2004Assignee: Hynix Semiconductor Inc.Inventors: Nam Kyeong Kim, Ki Seon Park, Dong Su Park, Byoung Kwon Ahn, Seung Kyu Han
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Patent number: 6812042Abstract: The present invention provides a ferroelectric memory device capable of suppressing a defect generation due to a charge impact and a method for fabricating the same. The ferroelectric memory device includes: a semiconductor substrate on which a transistor is formed; a semiconductor substrate structure having a transistor; a lower electrode formed on an interfacial insulation layer and connected to a source/drain region of the transistor; an isolating insulation layer on the interfacial insulation layer; a ferroelectric layer covering the isolating insulation layer and lower electrode; an oxygen vacancy compensation layer being formed on the ferroelectric layer and compensating an oxygen vacancy caused by deoxidization of a composition of the ferroelectric layer; and an upper electrode formed on the oxygen vacancy compensation layer.Type: GrantFiled: July 8, 2003Date of Patent: November 2, 2004Assignee: Hynix Semiconductor Inc.Inventors: Nam-Kyeong Kim, Soon-Yong Kweon, Seung-Jin Yeom
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Patent number: 6812089Abstract: The present invention is related to a method for fabricating a ferroelectric memory device effectively preventing a deformation and lift of a lower electrode caused by a different thermal expansion rate between the lower electrode and a inter layer dielectric film at a succeeding heat treatment process. The method for fabricating a ferroelectric memory device includes: forming a lower electrode on a predetermined surface of a semiconductor substrate; forming a metal oxide layer over a surface of the lower electrode and a surface of the semiconductor substrate; forming an inter layer dielectric film over the metal oxide layer; performing a blanket etching for the inter layer dielectric film and the metal oxide layer; and forming an opening having a predetermined depth.Type: GrantFiled: July 16, 2003Date of Patent: November 2, 2004Assignee: Hynix Semiconductor Inc.Inventors: Eun-Seok Choi, Nam-Kyeong Kim
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Publication number: 20040124453Abstract: The present invention provides a ferroelectric memory device capable of suppressing a defect generation due to a charge impact and a method for fabricating the same. The ferroelectric memory device includes: a semiconductor substrate on which a transistor is formed; a semiconductor substrate structure having a transistor; a lower electrode formed on an interfacial insulation layer and connected to a source/drain region of the transistor; an isolating insulation layer on the interfacial insulation layer; a ferroelectric layer covering the isolating insulation layer and lower electrode; an oxygen vacancy compensation layer being formed on the ferroelectric layer and compensating an oxygen vacancy caused by deoxidization of a composition of the ferroelectric layer; and an upper electrode formed on the oxygen vacancy compensation layer.Type: ApplicationFiled: July 8, 2003Publication date: July 1, 2004Inventors: Nam-Kyeong Kim, Soon-Yong Kweon, Seung-Jin Yeom
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Publication number: 20040126959Abstract: The present invention is related to a method for fabricating a ferroelectric memory device effectively preventing a deformation and lift of a lower electrode caused by a different thermal expansion rate between the lower electrode and a inter layer dielectric film at a succeeding heat treatment process. The method for fabricating a ferroelectric memory device includes: forming a lower electrode on a predetermined surface of a semiconductor substrate; forming a metal oxide layer over a surface of the lower electrode and a surface of the semiconductor substrate; forming an inter layer dielectric film over the metal oxide layer; performing a blanket etching for the inter layer dielectric film and the metal oxide layer; and forming an opening having a predetermined depth.Type: ApplicationFiled: July 16, 2003Publication date: July 1, 2004Inventors: Eun-Seok Choi, Nam-Kyeong Kim
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Patent number: 6747302Abstract: A ferroelectric memory device and a method for manufacturing the same is disclosed. Because a (BixLay)Ti3O12 (BLT) layer, which can be crystallized in relatively low temperature, is used in a capacitor, the electrical characteristics of the ferroelectric capacitor can be improved. The method for manufacturing ferroelectric memory device includes the steps of forming a first conductive layer for a bottom electrode on a semiconductor substrate, forming the (BixLay)Ti3O12 ferroelectric layer, wherein ‘x’ representing atomic concentration of Bi ranges from about 3.25 to about 3.35 and ‘y’ representing atomic concentration of La ranges from about 0.70 to about 0.90 and forming a second conductive layer for a top electrode on the (BixLay)Ti3O12 ferroelectric layer.Type: GrantFiled: April 26, 2002Date of Patent: June 8, 2004Assignee: Hynix Semiconductor Inc.Inventors: Nam-Kyeong Kim, Seung-Jin Yeom, Woo-Seok Yang, Soon-Yong Kweon
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Publication number: 20030205744Abstract: In the method for forming a capacitor of a nonvolatile semiconductor memory device, a TaON glue layer is formed over a semiconductor substrate, and a lower electrode is formed on the TaON glue layer. A ferroelectric film is then formed on the lower electrode, and an upper electrode is formed on the ferroelectric film.Type: ApplicationFiled: June 3, 2003Publication date: November 6, 2003Applicant: Hynix Semiconductor, Inc.Inventors: Nam Kyeong Kim, Ki Seon Park, Dong Su Park, Byoung Kwon Ahn, Seung Kyu Han
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Patent number: 6597029Abstract: In the method for forming a capacitor of a nonvolatile semiconductor memory device, a TaON glue layer is formed over a semiconductor substrate, and a lower electrode is formed on the TaON glue layer. A ferroelectric film is then formed on the lower electrode, and an upper electrode is formed on the ferroelectric film.Type: GrantFiled: June 14, 2001Date of Patent: July 22, 2003Assignee: Hynix Semiconductor Inc.Inventors: Nam Kyeong Kim, Ki Seon Park, Dong Su Park, Byoung Kwon Ahn, Seung Kyu Han
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Publication number: 20020160542Abstract: A ferroelectric memory device and a method for manufacturing the same is disclosed. Because a (BixLay)Ti3O12 (BLT) layer, which can be crystallized in relatively low temperature, is used in a capacitor, the electrical characteristics of the ferroelectric capacitor can be improved. The method for manufacturing ferroelectric memory device includes the steps of forming a first conductive layer for a bottom electrode on a semiconductor substrate, forming the (BixLay)Ti3O12 ferroelectric layer, wherein ‘x’ representing atomic concentration of Bi ranges from about 3.25 to about 3.35 and ‘y’ representing atomic concentration of La ranges from about 0.70 to about 0.90 and forming a second conductive layer for a top electrode on the (BixLay)Ti3O12 ferroelectric layer.Type: ApplicationFiled: April 26, 2002Publication date: October 31, 2002Applicant: Hynix Semiconductor Inc.Inventors: Nam-Kyeong Kim, Seung-Jin Yeom, Woo-Seok Yang, Soon-Young Kweon
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Patent number: 6455329Abstract: A method for fabricating a capacitor in a semiconductor device includes forming a semiconductor device having a source, a drain, and a gate on a semiconductor substrate, forming an interlayer insulating film having a contact hole exposing the source, forming a conductive layer in the contact hole, forming a lower electrode on the interlayer insulating film, inclusive of the conductive layer, coating an insulating material on the lower electrode for forming a dielectric film, subjecting the insulating material to a first rapid thermal annealing of a first temperature in a chamber, to form nuclei oriented along an a-b axis, subjecting the insulating material to a second rapid thermal annealing at a second temperature higher than the first temperature in the chamber, to grow the nuclei oriented along the a-b axis, to form a dielectric film, and forming an upper electrode on the dielectric film.Type: GrantFiled: December 20, 2001Date of Patent: September 24, 2002Assignee: Hynix Semiconductor Inc.Inventors: Nam Kyeong Kim, Seung Jin Yeom
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Patent number: 6417012Abstract: A semiconductor fabrication technique for forming a ferroelectric capacitor, in which the thermal burden is reduced by using an SBT-based ferroelectric thin film such as SrxBiyTa2O9 (‘SBT’) or SrxBiy(TaiNbj)2O9 (‘SBT(N)’) as the dielectric medium. The method includes the following steps. A strontium-bismuth-tantalum oxide film is formed on a semiconductor substrate, with a conductive film for a lower electrode having been formed on the semiconductor substrate (first step). An NH3 gas is flowed at a stabilizing step of a rapid thermal annealing so as to reduce organic materials bonded with metal elements of the strontium-bismuth-tantalum oxide film (second step). An oxide gas is flowed at a temperature of 450˜650° C. at an annealing step of the rapid thermal annealing so as to induce a perovskite nuclear formation in the strontium-bismuth-tantalum oxide film (third step).Type: GrantFiled: December 7, 2001Date of Patent: July 9, 2002Assignee: Hynix Semiconductor Inc.Inventors: Nam-Kyeong Kim, Woo-Seok Yang, Seung-Jin Yeom
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Publication number: 20020081752Abstract: A method for fabricating a capacitor in a semiconductor device includes forming a semiconductor device having a source, a drain, and a gate on a semiconductor substrate, forming an interlayer insulating film having a contact hole exposing the source, forming a conductive layer in the contact hole, forming a lower electrode on the interlayer insulating film, inclusive of the conductive layer, coating an insulating material on the lower electrode for forming a dielectric film, subjecting the insulating material to a first rapid thermal annealing of a first temperature in a chamber, to form nuclei oriented along an a-b axis, subjecting the insulating material to a second rapid thermal annealing at a second temperature higher than the first temperature in the chamber, to grow the nuclei oriented along the a-b axis, to form a dielectric film, and forming an upper electrode on the dielectric film.Type: ApplicationFiled: December 20, 2001Publication date: June 27, 2002Applicant: Hynix Semiconductor Inc.Inventors: Nam Kyeong Kim, Seung Jin Yeom