Abstract: A memory cell (101) includes a memory transistor (10A) having channel length L1 and channel width W1, and a plurality of select transistors (10B) each electrically being connected in series with the memory transistor and independently having channel length L2 and channel width W2, wherein each of the memory transistor and the plurality of select transistors includes an active layer (7A) formed from a common oxide semiconductor film, the memory transistor is a transistor which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg, and channel length L2 is greater than channel length L1.

Abstract: A semiconductor device includes a memory transistor (10A) which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg. The memory transistor (10A) includes a gate electrode (3), a metal oxide layer (7), a gate insulating film (5), and source and drain electrodes. The drain electrode (9d) has a multilayer structure which includes a first drain metal layer (9d1) and a second drain metal layer (9d2), the first drain metal layer (9d1) being made of a first metal whose melting point is not less than 1200° C., the second drain metal layer (9d2) being made of a second metal whose melting point is lower than that of the first metal. Part P of the drain electrode 9d extends over both the metal oxide layer (7) and the gate electrode (3) when viewed in a direction normal to a surface of the substrate.

Abstract: A semiconductor device (1001) includes: a first transistor (10A) having a first channel length L1 and a first channel width W1; and a second transistor (10B) having a second channel length L2 and a second channel width W2, wherein the first transistor (10A) and the second transistor (10B) include an active layer formed from a common oxide semiconductor film, the first transistor (10A) is a memory transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Isd depends on a gate voltage Vg to a resistor state where the drain current Isd does not depend on the gate voltage Vg, and the first channel length L1 is smaller than the second channel length L2.

Abstract: A circuit board has a through hole extending from a front surface to a rear surface. A press-fit terminal is press-fitted from the front surface into the through hole and is connected to a land, which is formed on a wall surface of the through hole. A support member supports the rear surface of the circuit board when the press-fit terminal is press-fitted into the through hole. A housing has a bottom portion and an opening, which is on the opposite side of the bottom portion. The circuit board is affixed to the housing to cover both the opening and the support member. The support member is held and interposed between the rear surface and an inner surface of the bottom portion.

Abstract: A memory cell (101) includes a memory transistor (10A) having channel length L1 and channel width W1, and a plurality of select transistors (10B) each electrically being connected in series with the memory transistor and independently having channel length L2 and channel width W2, wherein each of the memory transistor and the plurality of select transistors includes an active layer (7A) formed from a common oxide semiconductor film, the memory transistor is a transistor which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg, and channel length L2 is greater than channel length L1.

Abstract: A work state measurement device comprises an observation timing notifying unit which notifies observation starting timing and observation finishing timing as observation timing to an observer in every preliminarily set time interval, an observation state input unit in which the work state which is observed is divided into a plurality of work state items and an observation state record unit which weights work state items which are inputted in the observation input unit while from observation starting timing to observation finishing timing by information of the work state items which are inputted and records the work state items as observation states.

Abstract: Single perforating unit is enabled to perforate for file binders and to cut milling grooves, while with a simple structure file-binder storage and booklet-binding can be carried out reliably. Configurations include: a convey-in path for sequentially transferring sheets; a stacker for collating into bundles sheets from the convey-in path; and an adhesive-layer applicator for adding an adhesive layer to the spine-closure edge of sheet bundles from the stacker. A perforating unit is provided in along the convey-in path, and a control unit for controlling position and/or number of perforations made by the perforating unit is provided with (1) a first operation mode in which it effects the punching of a predetermined number of holes in the edge of sheets, and (2) a second operation mode in which it effects the formation of a predetermined number of crenulated grooves in the edge of sheets.

Abstract: A semiconductor device includes: a plurality of thin film transistors including a gate electrode, a gate dielectric layer, a semiconductor layer formed on the gate dielectric layer, and a source electrode and a drain electrode provided on the semiconductor layer; a source metal layer including a global line which supplies a common signal to the plurality of thin film transistors, the global line being made of the same electrically conductive film as the source electrode and drain electrode; and a dielectric protection layer covering the plurality of thin film transistors and the source metal layer. The source metal layer includes a lower layer and an upper layer stacked on a portion of the lower layer. The global line has a first layer structure including the lower layer and the upper layer, and at least a portion of each source electrode and of each drain electrode that is located on the semiconductor layer has a second layer structure including the lower layer but not including the upper layer.

Abstract: A semiconductor device (100A) includes a first metal layer (12) including a gate electrode (12g); a gate insulating layer (14) formed on the first metal layer; an oxide semiconductor layer (16) formed on the gate insulating layer; a second metal layer (18) formed on the oxide semiconductor layer; an interlayer insulating layer (22) formed on the second metal layer; and a transparent electrode layer (TE) including a transparent conductive layer (Tc). The oxide semiconductor layer includes a first portion (16a) and a second portion (16b) extending while crossing an edge of the gate electrode. The second metal layer includes a source electrode (18s) and a drain electrode (18d). The interlayer insulating layer does not include an organic insulating layer. The interlayer insulating layer includes a contact hole (22a) formed so as to overlap the second portion and an end of the drain electrode that is closer to the second portion.

Abstract: The present invention provides a non-volatile memory device using a memory transistor including an oxide semiconductor, capable of writing with low power consumption, without receiving an influence of deterioration of a selection transistor connected in series to the memory transistor. A memory cell 1 includes a memory transistor Qm, and first and second selection transistors Q1 and Q2. During a writing operation, the memory transistor Qm and the first selection transistor Q1 are set to the ON state, and the second selection transistor Q2 is set to the OFF state. A writing current is flown to a series circuit of the memory transistor Qm and the first selection transistor Q1. The memory transistor Qm is transited from a first state that indicates a transistor characteristic to a second state that indicates an ohmic resistance characteristic.

Abstract: Single perforating unit is enabled to perforate for file binders and to cut milling grooves, while with a simple structure file-binder storage and booklet-binding can be carried out reliably. Configurations include: a convey-in path for sequentially transferring sheets; a stacker for collating into bundles sheets from the convey-in path; and an adhesive-layer applicator for adding an adhesive layer to the spine-closure edge of sheet bundles from the stacker. A perforating unit is provided in along the convey-in path, and a control unit for controlling position and/or number of perforations made by the perforating unit is provided with (1) a first operation mode in which it effects the punching of a predetermined number of holes in the edge of sheets, and (2) a second operation mode in which it effects the formation of a predetermined number of crenulated grooves in the edge of sheets.

Abstract: The present invention provides a memory circuit including a memory element to which writing can be performed with a small current and a low voltage, i.e., low power consumption, and provides a non-volatile storage device that can easily reduce a chip size by using this memory circuit. A memory element 1 is a memory transistor having a transistor structure including a source electrode 14, a drain electrode 15, a gate electrode 11, and, a source region, a drain region, and a channel region made of a metal oxide semiconductor layer 13. The resistance property between the source and the drain shows a low resistance, and the memory transistor is changed to have an ohmic resistance property, regardless of a voltage application state of the gate electrode, by allowing a writing current with a density not less than a predetermined value to flow in the channel region to generate Joule heat.

Abstract: A vehicle warning sound emitting apparatus includes a warning sound emitting component and a controller. The warning sound emitting component selectively emits a warning sound that is audible outside of the vehicle. The controller controls the warning sound emitting component to emit the warning sound during a prescribed period that an engine sound is being emitted from an engine of the vehicle such that the engine sound and the warning sound are audible at a location outside the vehicle during the prescribed period when the controller is controlling the warning sound emitting component to switch between emitting the warning sound and refraining from emitting the warning sound based on a vehicle traveling condition.

Abstract: The present invention provides a non-volatile memory device using a memory transistor including an oxide semiconductor, capable of writing with low power consumption, without receiving an influence of deterioration of a selection transistor connected in series to the memory transistor. A memory cell 1 includes a memory transistor Qm, and first and second selection transistors Q1 and Q2. During a writing operation, the memory transistor Qm and the first selection transistor Q1 are set to the ON state, and the second selection transistor Q2 is set to the OFF state. A writing current is flown to a series circuit of the memory transistor Qm and the first selection transistor Q1. The memory transistor Qm is transited from a first state that indicates a transistor characteristic to a second state that indicates an ohmic resistance characteristic.

Abstract: Provided is a transistor element in which the state thereof is changed into that of a resistor with a small power consumption without migration and melting of the resistor due to a large current, and physical changes, such as breakdown of an insulating film due to high electric field application, and the state change can be used as a memory element. This metal oxide transistor is provided with: a semiconductor thin film formed of a metal oxide semiconductor; a source electrode and a drain electrode, which are in contact with the semiconductor thin film; and a gate electrode, which faces the semiconductor thin film with a gate insulating film therebetween.

Abstract: A semiconductor device that includes a substrate 37, a non-volatile memory (memory cell) 21 having a memory cell transistor (switching element) 33 and a floating gate electrode (memory storage part) 36, and a passivation insulating film (insulating layer) 40 and an organic polymer film (insulating layer) 41 both provided above the non-volatile memory 21, in which conductive wiring line layers (shielding part) 5a to 5c for shielding the floating gate electrode 36 are provided between the floating gate electrode 36 and both the passivation insulating film 40 and the organic polymer film 41 so that ions generated from the passivation insulating film 40 and the organic polymer film 41 can be prevented from reaching the floating gate electrode 36.

Abstract: The present invention provides a passenger guidance display system comprising a service managing apparatus configured to manage on-rail information and a service schedule of a train and a passenger guidance display apparatus provided in a station premise and configured to perform display of passenger guidance using service information of a train scheduled to arrive next transmitted from the service managing apparatus.

Abstract: A bipolar plate for a fuel cell comprises a substrate formed of stainless steel; an oriented amorphous carbon film formed at least on a surface of the substrate facing an electrode, and containing C as a main component, 3 to 20 at. % of N, and more than 0 at. % and not more than 20 at. % of H, and when the total amount of the C is taken as 100 at. %, the amount of C having an sp2 hybrid orbital (Csp2) being not less than 70 at. % and less than 100 at. %, and (002) planes of graphite being oriented along a thickness direction; a mixed layer generated in an interface between the substrate and the oriented amorphous carbon film and containing at least one kind of constituent atoms of each of the substrate and the oriented amorphous carbon film; and a plurality of projections protruding from the mixed layer into the oriented amorphous carbon film and having a mean length of 10 to 150 nm.

Abstract: A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively.

Abstract: The present invention provides a semiconductor device comprising: a silicon based semiconductor substrate provided with a step including an non-horizontal surface, a horizontal surface and a connection region for connecting the non-horizontal surface and the horizontal surface; a gate insulating film formed in at least a part of the step; and a gate electrode formed on the gate insulating film, wherein the entirety or a part of the gate insulating film is formed of a silicon oxynitride film that contains a rare gas element at a area density of 1010 cm?2 or more in at least a part of the silicon oxynitride film.