Abstract: A nonvolatile random access memory that can be mounted on a substrate during a standard CMOS process. A memory cell comprises: a first MIS transistor including a first semiconductor layer of a first conductivity type in an electrically floating state, first drain and source regions of a second conductivity type formed on the first semiconductor layer, and a first gate electrode formed over the first semiconductor layer via a first gate insulating film; and a second MIS transistor including a second semiconductor layer of the first conductivity type isolated from the first semiconductor layer, second drain and source regions of the second conductivity type formed on the second semiconductor layer, a second gate electrode formed over the second semiconductor layer via a second gate insulating film. The first and second gate electrodes are electrically connected to each other so as to form a floating gate in an electrically floating state.

Abstract: A method of transforming a geographic coordinate to a geographic location code includes the steps of: retrieving a latitude value and a longitude value of the geographic coordinate; quantizing the latitude value to a first integer value; quantizing the longitude value to a second integer value; converting the first integer value to a first code string, said first code string including a first digit representing a non-numeric character, a second digit representing a non-numeric character, and a third digit representing a numeric character; converting the second integer value to a second code string, said second code string including a fourth digit representing a non-numeric character, a fifth digit representing a non-numeric character, and a sixth digit representing a numeric character; and combining the first code string and the second code string to obtain the geographic location code having a fixed pattern of radix in a mixed radix notation system representation.

Abstract: A method of transforming a geographic coordinate to a geographic location code includes the steps of: retrieving a latitude value and a longitude value of the geographic coordinate; quantizing the latitude value to a first integer value; quantizing the longitude value to a second integer value; converting the first integer value to a first code string, said first code string including a first digit representing a non-numeric character, a second digit representing a non-numeric character, and a third digit representing a numeric character; converting the second integer value to a second code string, said second code string including a fourth digit representing a non-numeric character, a fifth digit representing a non-numeric character, and a sixth digit representing a numeric character; and combining the first code string and the second code string to obtain the geographic location code having a fixed pattern of radix in a mixed radix notation system representation.

Abstract: To provide a trimming apparatus that does not stain a fore edge end by an adhesive adhering to a blade receiving surface in trimming a bunch of sheets subjected to bookbinding using the adhesive, the trimming apparatus has a transport path 33 for feeding a bunch of sheets to a predetermined trimming position G, trimming blade 65x disposed in the trimming position, bunch position changing means 64 disposed in the transport path to change a position of the bunch of sheets in the trimming position, blade receiving member 67 disposed opposite to the trimming blade with the bunch of sheets in the transport path therebetween, and driving means Mc traveling between a cut position Cp for bringing the trimming blade into contact with the blade receiving member and a spaced waiting position Wp, where in the blade receiving member are set first and second, at least two, blade receiving areas with different blade receiving surfaces coming into contact with the trimming blade, while shift means MS for shifting positions b

Abstract: A nonvolatile semiconductor memory device capable of preventing the disturb phenomenon that could become a serious problem as the nonvolatile memory having a virtual grounding bit line is miniaturized includes a program row voltage application circuit for applying a predetermined program row voltage to the selected word line in programming in the selected memory cell, a program column voltage application circuit for applying a ground voltage to one of a pair of selected bit lines and applying a predetermined program column voltage to the other of the selected bit lines in programming; and a counter voltage application circuit for applying a counter voltage of an intermediate voltage between the ground voltage and program column voltage, to an adjacent unselected bit line not connected to the selected memory cell in the first and second bit lines and adjacent to the selected bit line to which the program column voltage is applied.

Abstract: A nonvolatile semiconductor memory device capable of improving injection efficiency and simplifying manufacturing process is provided. The device comprises a memory cell having second conductive type of first impurity diffusion area and second impurity diffusion area on a first conductive type of semiconductor substrate, between the first and second impurity diffusion areas, a first laminate section formed by laminating a first insulating film, a charge storage layer, a second insulating film and a first gate electrode in this order from the bottom, and a second laminate section formed by laminating a third insulating film and a second gate electrode in this order from the bottom, wherein an area sandwiched between the first and second laminate sections is the second conductive type of a third impurity diffusion area having impurity density lower than that of the first and second impurity diffusion areas and not higher than 5×1012 ions/cm2.

Abstract: In a displacement-type marine vessel which travels in a velocity range where the Froude number is smaller than the last hump, a stern shape includes knuckle lines connecting knuckle points, provided on the surface of the cross sections of the hull at the stern, continuously from a starting point in front of a propeller to an end point behind the propeller in the fore-and-aft direction of the hull, and a frame line located inside the knuckle line in the width direction of the hull which has a dome shape with upward curvature, the length of the hull portion which has the dome shape is 10% or more of the entire hull length or at least the diameter of the propeller, and the position of the starting point in the width direction of the hull is outside the position of the radius of the propeller.

Abstract: A virtual ground type semiconductor memory device comprises: a memory cell array in which nonvolatile memory cells each including a first electrode, a pair of second electrodes, and a charge retention part are arranged in row and column directions like a matrix; a read circuit for selecting a pair of the first and second bit lines connected to a selected memory cell to be read, applying first and second read voltages to the selected first and second bit lines, respectively, and detecting a magnitude of a memory cell current flowing in the selected memory cell, at the time of reading; a voltage applying means for applying the second read voltage to a second adjacent bit line adjacent to the selected second bit line on the opposite side of the first bit line; and a short-circuit means for short-circuiting the selected second bit line and the second adjacent bit line.

Abstract: A nonvolatile memory cell that can be mounted in a CMOS manufacturing process, and is capable of implementing high level of programming, reading and erasing ability. The memory cell is configured by a MOS transistor including two N-type first impurity diffusion layers formed separately on a P-type semiconductor substrate, and a first gate electrode formed above a first cannel region sandwiched by both diffusion layers through a first gate insulation film, a first capacitor comprising P-type second impurity diffusion layers formed on a well, and a second gate electrode formed above the diffusion layer through a second gate insulation film, and a second capacitor comprising the well adjacent to the second impurity diffusion layer, and a third gate electrode formed above the well through a third gate insulation film, wherein a different voltage can be applied to each of the capacitors.

Abstract: A nonvolatile semiconductor memory device capable of preventing the disturb phenomenon that could become a serious problem as the nonvolatile memory having a virtual grounding bit line is miniaturized comprises a program row voltage application circuit for applying a predetermined program row voltage to the selected word line in programming in the selected memory cell, a program column voltage application circuit for applying a ground voltage to one of a pair of selected bit lines and applying a predetermined program column voltage to the other of the selected bit lines in programming; and a counter voltage application circuit for applying a counter voltage of an intermediate voltage between the ground voltage and program column voltage, to an adjacent unselected bit line not connected to the selected memory cell in the first and second bit lines and adjacent to the selected bit line to which the program column voltage is applied.

Abstract: Single perforating unit is enabled to perforate for file binders and to cut milling grooves, while with a simple structure file-binder storage and booklet-binding can be carried out reliably. Configurations include: a convey-in path for sequentially transferring sheets; a stacker for collating into bundles sheets from the convey-in path; and an adhesive-layer applicator for adding an adhesive layer to the spine-closure edge of sheet bundles from the stacker. A perforating unit is provided in along the convey-in path, and a control unit for controlling position and/or number of perforations made by the perforating unit is provided with (1) a first operation mode in which it effects the punching of a predetermined number of holes in the edge of sheets, and (2) a second operation mode in which it effects the formation of a predetermined number of crenulated grooves in the edge of sheets.

Abstract: A nonvolatile semiconductor memory device and its writing method for reducing a writing rate variation without changing a voltage condition applied for each memory cell in writing operation is provided. The device comprises a memory cell array configuration where each drain of the memory cells on the same column is connected to a first bit line via a second bit line and a bit line contact, and the shortest distance from each drain of the memory cells to the bit line contact varies according to a location of the memory cell in the column direction. The method includes a writing operation carried out sequentially from the nearest memory cell to the bit line contact, upon writing continuously so that the memory cell current becomes small for all or some of the memory cells on the same column between the two adjacent bit line contacts in the column direction.

Abstract: A virtual ground type semiconductor memory device comprises: a memory cell array in which nonvolatile memory cells each including a first electrode, a pair of second electrodes, and a charge retention part are arranged in row and column directions like a matrix; a read circuit for selecting a pair of the first and second bit lines connected to a selected memory cell to be read, applying first and second read voltages to the selected first and second bit lines, respectively, and detecting a magnitude of a memory cell current flowing in the selected memory cell, at the time of reading; a voltage applying means for applying the second read voltage to a second adjacent bit line adjacent to the selected second bit line on the opposite side of the first bit line; and a short-circuit means for short-circuiting the selected second bit line and the second adjacent bit line.

Abstract: There is provided a nonvolatile semiconductor memory device capable of accelerating writing time and avoiding readout errors of information by eliminating variation in threshold voltage of unselected memory cells. In a nonvolatile semiconductor memory device having a memory cell array with memory cells capable of erasing and programming information, the memory cells store one data value selected from the same number of data values as programming distribution ranges, associated with that the electrical attribute belongs to any one of the more than one programming distribution ranges. The device comprises an erasure means for erasing the selected memory cell to be erased so that its electrical attribute belongs to a erasure distribution range not overlapping any of the programming distribution ranges and a programming means for programming an erased memory cell to be programmed so that its electrical attribute belongs to any one of the programming distribution ranges.

Abstract: A nonvolatile memory cell that can be mounted in a CMOS manufacturing process, and is capable of implementing high level of programming, reading and erasing ability. The memory cell is configured by a MOS transistor comprising two N-type first impurity diffusion layers formed separately on a P-type semiconductor substrate, and a first gate electrode formed above a first cannel region sandwiched by both diffusion layers through a first gate insulation film, a first capacitor comprising P-type second impurity diffusion layers formed on a well, and a second gate electrode formed above the diffusion layer through a second gate insulation film, and a second capacitor comprising the well adjacent to the second impurity diffusion layer, and a third gate electrode formed above the well through a third gate insulation film, wherein a different voltage can be applied to each of the capacitors.

Abstract: A nonvolatile semiconductor memory device capable of improving injection efficiency and simplifying manufacturing process is provided. The device comprises a memory cell having second conductive type of first impurity diffusion area and second impurity diffusion area on a first conductive type of semiconductor substrate, between the first and second impurity diffusion areas, a first laminate section formed by laminating a first insulating film, a charge storage layer, a second insulating film and a first gate electrode in this order from the bottom, and a second laminate section formed by laminating a third insulating film and a second gate electrode in this order from the bottom, wherein an area sandwiched between the first and second laminate sections is the second conductive type of a third impurity diffusion area having impurity density lower than that of the first and second impurity diffusion areas and not higher than 5×1012 ions/cm2.

Abstract: A semiconductor memory device comprises: a plurality of memory elements; at least one bit line, wherein a memory operation is performed via at least a portion of the bit line with respect to at least one of the plurality of memory elements; and a load resistance regulating circuit for changing a resistance value to reduce or eliminate a difference in bit line load resistance depending on a position of the memory element.

Abstract: Method for determining the number of applications of erasing pulses, including extracting two pairs of the accumulated number of the erasing pulses Np and the ratio Re of the number of erased memory cells in the target block to be erased after the accumulated number of the erasing pulses Np has been applied, converting the two ratios Re into normalized variables S(Re) through normalizing the random variables of the normal distribution probability with standard deviations, converting the two accumulated numbers of the erasing pulses Np into common logarithms Log(Np), calculating a common logarithm Log(Nt) through extrapolating from two sets of coordinates [Log(Np), S(Re)], and determining the number of applications of the remaining erasing pulses so that the extrapolation erasing pulse number Nt is the target accumulated number of applications of erasing pulses.

Abstract: There is provided a nonvolatile semiconductor memory device capable of accelerating writing time and avoiding readout errors of information by eliminating variation in threshold voltage of unselected memory cells. In a nonvolatile semiconductor memory device having a memory cell array with memory cells capable of erasing and programming information, the memory cells store one data value selected from the same number of data values as programming distribution ranges, associated with that the electrical attribute belongs to any one of the more than one programming distribution ranges. The device comprises an erasure means for erasing the selected memory cell to be erased so that its electrical attribute belongs to a erasure distribution range not overlapping any of the programming distribution ranges and a programming means for programming an erased memory cell to be programmed so that its electrical attribute belongs to any one of the programming distribution ranges.

Abstract: A nonvolatile semiconductor memory device and its writing method for reducing a writing rate variation without changing a voltage condition applied for each memory cell in writing operation is provided. The device comprises a memory cell array configuration where each drain of the memory cells on the same column is connected to a first bit line via a second bit line and a bit line contact, and the shortest distance from each drain of the memory cells to the bit line contact varies according to a location of the memory cell in the column direction. The method includes a writing operation carried out sequentially from the nearest memory cell to the bit line contact, upon writing continuously so that the memory cell current becomes small for all or some of the memory cells on the same column between the two adjacent bit line contacts in the column direction.