Patents by Inventor Naoki Ueda
Naoki Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140356764Abstract: An amorphous carbon film contains carbon as a main component, not more than 30 at. % of hydrogen, not more than 20 at. % of nitrogen and not more than 3 at. % of oxygen (all excluding 0 at. %), and when the total amount of the carbon is taken as 100 at. %, the amount of carbon having an sp2 hybrid orbital is not less than 70 at. % and less than 100 at. %. Nitrogen and oxygen are concentrated on a surface side of the film and when detected from a surface layer by X-ray photoelectron spectroscopy, oxygen content ratio is not less than 4 at. % and not more than 15 at. % and nitrogen content ratio is not less than 10 at. % and not more than 30 at. %. The amorphous carbon film attains both electric conductivity and hydrophilicity and exhibits suitable surface characteristics to a fuel cell bipolar plate, etc.Type: ApplicationFiled: January 25, 2013Publication date: December 4, 2014Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashi Iseki, Kazuyuki Nakanishi, Yasuhiro Ozawa, Naoki Ueda, Masafumi Koizumi
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Publication number: 20140334227Abstract: The present invention provides a memory circuit including a memory element to which writing can be performed with a small current and a low voltage, i.e., low power consumption, and provides a non-volatile storage device that can easily reduce a chip size by using this memory circuit. A memory element 1 is a memory transistor having a transistor structure including a source electrode 14, a drain electrode 15, a gate electrode 11, and, a source region, a drain region, and a channel region made of a metal oxide semiconductor layer 13. The resistance property between the source and the drain shows a low resistance, and the memory transistor is changed to have an ohmic resistance property, regardless of a voltage application state of the gate electrode, by allowing a writing current with a density not less than a predetermined value to flow in the channel region to generate Joule heat.Type: ApplicationFiled: November 12, 2012Publication date: November 13, 2014Inventor: Naoki Ueda
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Patent number: 8767136Abstract: In a display device, a liquid crystal capacitive element is sandwiched between a pixel electrode and an opposite electrode. The pixel electrode, one end of a first switch circuit, one end of a second switch circuit and a first terminal of a second transistor form an internal node. The other terminals of the first switch circuit and the second switch circuit are connected to a source line. The second switch circuit is a series circuit composed of a first transistor and a diode. A control terminal of the first transistor, a second terminal of the second transistor and one end of a boost capacitive element form an output node. The other end of the boost capacitive element and the control terminal of the second transistor are connected to a boost line and a reference line, respectively.Type: GrantFiled: August 29, 2011Date of Patent: July 1, 2014Assignee: Sharp Kabushiki KaishaInventors: Naoki Ueda, Yoshimitsu Yamauchi
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Patent number: 8654291Abstract: A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively.Type: GrantFiled: October 21, 2010Date of Patent: February 18, 2014Assignee: Sharp Kabushiki KaishaInventors: Naoki Ueda, Yoshimitsu Yamauchi, Fumiki Nakano
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Patent number: 8610197Abstract: Provided is a nonvolatile memory 10 having a selective gate SG formed below a silicon layer 14, which is to be a channel region formed between a source region S and a drain region D of a transistor, through a gate insulating film 15 between the silicon layer and the selective gate, a floating gate FG formed on a part over the silicon layer 14 through a gate insulating film 16, and a control gate CG connected to the floating gate FG. The selective gate SG has one end overlapping the source region S through the gate insulating film 15, and the floating gate FG has one end overlapping the drain region D through the gate insulating film 16, and the other end separated from the source region S and overlapping the silicon layer 14 through the gate insulating film 16. Thus, a nonvolatile memory whose performance is not deteriorated even when it is formed on an insulating substrate having a low heat dissipating characteristic can be achieved.Type: GrantFiled: December 14, 2009Date of Patent: December 17, 2013Assignee: Sharp Kabushiki KaishaInventors: Naoki Ueda, Yoshimitsu Yamauchi
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Patent number: 8576628Abstract: A nonvolatile random access memory that can be mounted on a substrate during a standard CMOS process. A memory cell comprises: a first MIS transistor including a first semiconductor layer of a first conductivity type in an electrically floating state, first drain and source regions of a second conductivity type formed on the first semiconductor layer, and a first gate electrode formed over the first semiconductor layer via a first gate insulating film; and a second MIS transistor including a second semiconductor layer of the first conductivity type isolated from the first semiconductor layer, second drain and source regions of the second conductivity type formed on the second semiconductor layer, a second gate electrode formed over the second semiconductor layer via a second gate insulating film. The first and second gate electrodes are electrically connected to each other so as to form a floating gate in an electrically floating state.Type: GrantFiled: January 6, 2009Date of Patent: November 5, 2013Assignee: Sharp Kabushiki KaishaInventor: Naoki Ueda
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Publication number: 20130286001Abstract: A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively.Type: ApplicationFiled: October 5, 2011Publication date: October 31, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Fumiki Nakano, Naoki Ueda, Yoshimitsu Yamauchi
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Publication number: 20130270249Abstract: An apparatus for controlling a vehicle, which includes: a battery (3) capable of being charged from an external power source (EPS); a power generation unit (PGU) capable of charging the battery (3); an electric heater (12) configured to produce heat with electric power from an electric power source; a heater core (11) configured to heat air by using any one of waste heat from the power generation unit (PGU) and the electric heater (12); and a controller (19) configured to perform control for selectively using the waste heat from the power generation unit (PGU) and the electric heater (12) as a heat source of the heater core (11) when the vehicle is parked.Type: ApplicationFiled: November 22, 2011Publication date: October 17, 2013Inventors: Keisuke Suzuki, Yuki Nakajima, Naoki Ueda
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Publication number: 20130222724Abstract: In a display device, a liquid crystal capacitive element is sandwiched between a pixel electrode and an opposite electrode. The pixel electrode, one end of a first switch circuit, one end of a second switch circuit and a first terminal of a second transistor form an internal node. The other terminals of the first switch circuit and the second switch circuit are connected to a source line. The second switch circuit is a series circuit composed of a first transistor and a diode. A control terminal of the first transistor, a second terminal of the second transistor and one end of a boost capacitive element form an output node. The other end of the boost capacitive element and the control terminal of the second transistor are connected to a boost line and a reference line, respectively.Type: ApplicationFiled: August 29, 2011Publication date: August 29, 2013Inventors: Naoki Ueda, Yoshimitsu Yamauchi
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Publication number: 20130097025Abstract: The present invention provides a passenger guidance display system comprising a service managing apparatus configured to manage on-rail information and a service schedule of a train and a passenger guidance display apparatus provided in a station premise and configured to perform display of passenger guidance using service information of a train scheduled to arrive next transmitted from the service managing apparatus.Type: ApplicationFiled: August 6, 2010Publication date: April 18, 2013Applicant: Mitsubishi Electric CorporationInventor: Naoki Ueda
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Patent number: 8398354Abstract: A bookbinding apparatus for trimming sheets includes an adhesive applying device for applying adhesive to a back of the sheets; a trimming blade disposed in a trimming position; a bunch position changing device disposed in a transport path to change a position of the sheets in the trimming position; a blade receiving member having at least first and second blade receiving areas with different blade receiving surfaces contacting with the trimming blade; a driving device positioning the trimming blade between a cut position for bringing the trimming blade into contact with the blade receiving member and a spaced waiting position; a shift device selectively shifting one of the first and second blade receiving areas to a predetermined trimming position, and a control device for controlling the shift means and the driving means.Type: GrantFiled: April 30, 2010Date of Patent: March 19, 2013Assignee: Nisca CorporationInventors: Kazuhide Sano, Hideki Orii, Keiichi Nagasawa, Sei Takahashi, Naoki Ueda, Suguru Maruyama
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Publication number: 20130033374Abstract: A vehicle warning sound emitting apparatus includes a warning sound emitting component and a controller. The warning sound emitting component to selectively emits a warning sound that is audible outside of the vehicle. The controller controls the warning sound emitting component to emit the warning sound during a prescribed period that an engine sound is being emitted from an engine of the vehicle such that the engine sound and the warning sound are audible at a location outside the vehicle during the prescribed period when the controller is controlling the warning sound emitting component to switch between emitting the warning sound and refraining from emitting the warning sound based on a vehicle traveling condition.Type: ApplicationFiled: May 23, 2011Publication date: February 7, 2013Applicant: NISSAN MOTOR CO., LTD.Inventors: Yuki Nakajima, Keisuke Suzuki, Naoki Ueda
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Publication number: 20130009163Abstract: A semiconductor device that includes a substrate 37, a non-volatile memory (memory cell) 21 having a memory cell transistor (switching element) 33 and a floating gate electrode (memory storage part) 36, and a passivation insulating film (insulating layer) 40 and an organic polymer film (insulating layer) 41 both provided above the non-volatile memory 21, in which conductive wiring line layers (shielding part) 5a to 5c for shielding the floating gate electrode 36 are provided between the floating gate electrode 36 and both the passivation insulating film 40 and the organic polymer film 41 so that ions generated from the passivation insulating film 40 and the organic polymer film 41 can be prevented from reaching the floating gate electrode 36.Type: ApplicationFiled: November 4, 2010Publication date: January 10, 2013Applicant: SHARP KABUSHIKI KAISHAInventor: Naoki Ueda
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Patent number: 8310638Abstract: Disclosed is a display device that can achieve a reduction of power consumption without deteriorating the aperture ratio. A liquid crystal capacitance element (Clc) is formed by being sandwiched between a pixel electrode (20) and an opposite electrode (80). The pixel electrode (20), one end of a first switching circuit (22), one end of a second switching circuit (23), and the first terminal of a second transistor (T2) form an internal node (N1). The other end of the first switching circuit (22) and the other end of the second switching circuit (23) are connected to a source line (SL). The second switching circuit (23) includes a series circuit of a transistor (T1) and a diode (D1), and an output node (N2) is formed of the control terminal of the transistor (T1), the second terminal of the transistor (T2), and one end of a boost capacitance element (Cbst).Type: GrantFiled: July 22, 2010Date of Patent: November 13, 2012Assignee: Sharp Kabushiki KaishaInventors: Yoshimitsu Yamauchi, Naoki Ueda, Fumiki Nakano
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Publication number: 20120231374Abstract: A bipolar plate for a fuel cell comprises a substrate formed of stainless steel; an oriented amorphous carbon film formed at least on a surface of the substrate facing an electrode, and containing C as a main component, 3 to 20 at. % of N, and more than 0 at. % and not more than 20 at. % of H, and when the total amount of the C is taken as 100 at. %, the amount of C having an sp2 hybrid orbital (Csp2) being not less than 70 at. % and less than 100 at. %, and (002) planes of graphite being oriented along a thickness direction; a mixed layer generated in an interface between the substrate and the oriented amorphous carbon film and containing at least one kind of constituent atoms of each of the substrate and the oriented amorphous carbon film; and a plurality of projections protruding from the mixed layer into the oriented amorphous carbon film and having a mean length of 10 to 150 nm.Type: ApplicationFiled: December 24, 2010Publication date: September 13, 2012Applicant: Toyota Jidosha Kabushiki KaishaInventors: Takashi Iseki, Kazuyuki Nakanishi, Yasuhiro Ozawa, Yuka Yamada, Hajime Hasegawa, Masafumi Koizumi, Katsutoshi Fujisawa, Naoki Ueda, Hirohiko Hisano
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Publication number: 20120218246Abstract: A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively.Type: ApplicationFiled: October 21, 2010Publication date: August 30, 2012Applicant: Sharp Kabushiki KatshaInventors: Naoki Ueda, Yoshimitsu Yamauchi, Fumiki Nakano
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Publication number: 20120212521Abstract: Disclosed is a display device that can achieve a reduction of power consumption without deteriorating the aperture ratio. A liquid crystal capacitance element (Clc) is formed by being sandwiched between a pixel electrode (20) and an opposite electrode (80). The pixel electrode (20), one end of a first switching circuit (22), one end of a second switching circuit (23), and the first terminal of a second transistor (T2) form an internal node (N1). The other end of the first switching circuit (22) and the other end of the second switching circuit (23) are connected to a source line (SL). The second switching circuit (23) includes a series circuit of a transistor (T1) and a diode (D1), and an output node (N2) is formed of the control terminal of the transistor (T1), the second terminal of the transistor (T2), and one end of a boost capacitance element (Cbst).Type: ApplicationFiled: July 22, 2010Publication date: August 23, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Yoshimitsu Yamauchi, Naoki Ueda, Fumiki Nakano
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Patent number: 8183647Abstract: The present invention provides a semiconductor device comprising: a silicon based semiconductor substrate provided with a step including an non-horizontal surface, a horizontal surface and a connection region for connecting the non-horizontal surface and the horizontal surface; a gate insulating film formed in at least a part of the step; and a gate electrode formed on the gate insulating film, wherein the entirety or a part of the gate insulating film is formed of a silicon oxynitride film that contains a rare gas element at a area density of 1010 cm?2 or more in at least a part of the silicon oxynitride film.Type: GrantFiled: December 11, 2003Date of Patent: May 22, 2012Assignees: Sharp Kabushiki KaishaInventors: Tadahiro Omi, Naoki Ueda
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Publication number: 20110303964Abstract: Provided is a nonvolatile memory 10 having a selective gate SG formed below a silicon layer 14, which is to be a channel region formed between a source region S and a drain region D of a transistor, through a gate insulating film 15 between the silicon layer and the selective gate, a floating gate FG formed on a part over the silicon layer 14 through a gate insulating film 16, and a control gate CG connected to the floating gate FG. The selective gate SG has one end overlapping the source region S through the gate insulating film 15, and the floating gate FG has one end overlapping the drain region D through the gate insulating film 16, and the other end separated from the source region S and overlapping the silicon layer 14 through the gate insulating film 16. Thus, a nonvolatile memory whose performance is not deteriorated even when it is formed on an insulating substrate having a low heat dissipating characteristic can be achieved.Type: ApplicationFiled: December 14, 2009Publication date: December 15, 2011Applicant: SHARP KABUSHIKI KAISHAInventors: Naoki Ueda, Yoshimitsu Yamauchi
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Patent number: 8028636Abstract: A stern shape of a displacement-type marine vessel enables reduction of the hull resistance and prevents propeller cavitation. The displacement-type marine vessel which travels in a velocity range in which the Froude number is smaller than the last hump and the stern includes knuckle lines connecting knuckle points provided on the surface of the hull, from a starting point in front of a propeller to an end point behind the propeller. A portion of the stern located inside the knuckle line in the direction of the width of the hull has a dome shape with upward curvature, and the length of the portion which has the dome shape is set to 10% or more of the entire hull length or at least the diameter of the propeller.Type: GrantFiled: January 30, 2008Date of Patent: October 4, 2011Assignee: Mitsubishi Heavy Industries, Ltd.Inventors: Reiko Takashima, Makoto Nishigaki, Toshinobu Sakamoto, Naoki Ueda, Kenichi Yamamoto